The increase of electronics in road vehicles comes along with a broad variety of possibilitiesin terms of safety, handling and comfort for the users. A rising complexityof the vehicle subsystems and components accompanies this development and has tobe managed by increased electronic control. More potential elements, such as sensors,actuators or software codes, can cause a failure independently or by mutually influencingeach other. There is a need of a structured approach to sort the faults from avehicle dynamics stability perspective.This thesis tries to solve this issue by suggesting a fault classification method and faulttolerantcontrol strategies. Focus is on typical faults of the electric driveline and thecontrol system, however mechanical and hydraulic faults are also considered. Duringthe work, a broad failure mode and effect analysis has been performed and the faultshave been modeled and grouped based on the effect on the vehicle dynamic behaviour.A method is proposed and evaluated, where faults are categorized into different levelsof controllability, i. e. levels on how easy or difficult it is to control a fault for the driver,but also for a control system.Further, fault-tolerant control strategies are suggested that can handle a fault with acritical controllability level. Two strategies are proposed and evaluated based on thecontrol allocation method and an electric vehicle with typical faults. It is shown thatthe control allocation approaches give less critical trajectory deviation compared to noactive control and a regular Electronic Stability Control algorithm.To conclude, this thesis work contributes with a methodology to analyse and developfault-tolerant solutions for electric vehicles with improved traffic safety. / <p>QC 20131010</p>

As VLSI circuits continue to have more and more transistors over time, the question of not only how to use, but how to manage the complexity of so many transistors becomes increasingly important. Four hypothesis are given for the design of a system that scales-up as transistors continue to shrink. An architecture is presented that satisfies these hypothesis, and the motivation behind the hypothesis is further explained. The use of this architecture's unique features to implement an efficient, defect-tolerant parallel bootstrap system is discussed. A detailed methodology for implementing this system in vivo is described. A sample problem--simulation of heat flow--is presented, and its solution using the proposed architecture is described in detail. A comparison is made between the proposed architecture and a set of contemporary architectures, and the former is shown to have desirable performance in a number of areas. Conclusion are given, and plans for future work are presented. / Ph. D.

Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases. To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Recon- figurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric. FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A iii significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria.