In recent decades, transient faults have become a critical issue in modernelectronic devices. Therefore, many fault-tolerant techniques have been proposedto increase system reliability, such as active redundancy, which can beimplemented in both space and time dimensions. The main challenge of activeredundancy is to introduce the minimal overhead of redundancy and to schedulethe tasks. In many pervious works, perfect fault detectors are assumed to simplifythe problem. However, the induced resource and time overheads of suchfault detectors make them impractical to be implemented. In order to tacklethe problem, an alternative approach was proposed based on imperfect faultdetectors. So far, only software implementation is studied for the proposed imperfectfault detection approach. In this thesis, we take hardware-acceleration intoconsideration. Field-programmable gate array (FPGA) is used to accommodatetasks in hardware. In order to utilize the FPGA resources efficiently, themapping and the selection of fault detectors for each task replica have to be carefullydecided. In this work, we present two optimization approaches consideringtwo FPGA technologies, namely, statically reconfigurable FPGA and dynamicallyreconfigurable FPGA respectively. Both approaches are evaluated andcompared with the proposed software-only approach by extensive experiments.

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This work deals with the design of a small hydro secured control system. The secured control system itself belongs to the Fault Tolerant Systems category. At first the requirements on small hydro control system are discussed. Then the introduction into the basics of Fault Tolerant System theory is given. The requirements on small hydro control system and basics of Fault Tolerant Systems are basis for specification of secured control system which design and construction is the main objective of this work.

Tato práce popisuje navrženou metodologii pro návrh systémů odolných proti poruchám v FPGA schopnou ochránit systém před projevy přechodných a trvalých poruch. Oprava přechodné poruchy je prováděna částečnou dynamickou rekonfigurací. Oprava omezeného počtu trvalých poruch je založena na použití odolných architektur využívajících menší množství zdrojů než předchozí použitá architektura. Vadná část FPGA tak není dále využívána. Tato technika je založena na použití předkompilovaných konfigurací uložených v externí paměti. Pro snížení paměťových nároků pro uložení konfiguračních bitových posloupností je použita technika relokace.

In this Master thesis a new framework for achieving fault tolerance in mechatronic systems is studied. The framework is called service-based fault tolerant control and has the advantage of being completely decentralized and modular and therefore scales very well to large system sizes. First, a method is presented for designing the signal-flow architecture of mechatronic systems of real-life size and complexity. The result is a small set of generic building blocks in the form of design patterns, a concept that has gained widespread popularity in the field of software architecture. Best practises are then established for how each of the design patterns can be extended to support fault tolerance through diagnosis and reconfiguration according to the service-based framework. These extended design patterns can be used either to aid in the construction of new and more complex mechatronic systems or as a methodology for applying service-based fault tolerant control on large existing systems. The presented methods for designing and modelling large-scale mechatronic systems have the advantages of being applicable to a large class of mechatronic systems, being easy to apply without expert knowledge, as well as having the potential for being automated in the future. Finally, a case-study demonstrates how the new methods can be used to construct a fault tolerance architecture for a real-life automotive system currently used by Scania CV AB. As a part of this study a mathematical model for the system was also constructed and implemented. The model can be used for analysis during the development phase as well as troubleshooting in a repair workshop.

Cette thèse s'inscrit dans un contexte où chaque saut technologique, voit apparaitre des circuits intégrés produits de plus en plus tôt dans la phase de qualification et où la technologie de ces circuits intégrés se rapproche de plus en plus des limitations physiques de la matière. Malgré des contre-mesures technologiques, on se retrouve devant un taux de défaillance grandissant ce qui crée des conditions favorables au retour des techniques de tolérance aux fautes sur les circuits intégrés non critiques.La densité d'intégration atteinte aujourd'hui nous permet de considérer les réseaux reconfigurables de processeur comme des architectures SoC d'avenir. En effet, l'homogénéité de ces architectures laisse entrevoir des reconfigurations possibles de la plateforme qui permettraient d'assurer une qualité de service et donc une fiabilité minimum en présence de défauts. Ainsi, de nouvelles solutions de protection doivent être proposées pour garantir le bon fonctionnement des circuits non plus uniquement au niveau de quelques sous-fonctionnalités critiques mais au niveau architecture système lui-même.En s'appuyant sur ces prérogatives, nous présentons une méthode de protection distribuée et dynamique innovatrice, D-Scale. La méthode consiste à détecter, isoler et recouvrir les systèmes en présence d'erreurs de type « crash ». La détection des erreurs qui ont pour conséquence un « crash » de la plateforme est basée sur un mécanisme de messages de diagnostique échangés entre les unités de traitement. La phase de recouvrement est quant à elle basée sur un mécanisme permettant la reconfiguration de la plateforme de manière autonome. Une implémentation de cette protection matérielle et logicielle est proposée. Le coût de protection est réduit afin d'être intégré dans de futures architectures multiprocesseurs. Finalement, un outil d'évaluation d'impacte des fautes sur la plateforme est aussi étudié afin de valider l'efficacité de la protection. / This thesis is placed in a context where, for each technology node, integrated circuits are design at an earlier stage in the qualification process and where the CMOS technology appears to be closer to the silicon physical limitations. Despite technological countermeasure, we face an increase in the failure rate which creates conditions in favor of the return of fault-tolerant techniques for non-critical integrated circuits.Nowadays, we have reached such an integration density that we can consider the reconfigurable processor array as future SoC architectures. Indeed, these homogenous architectures suggest possible platform reconfigurations that would ensure quality of service and consequently a minimum reliability in presence of defects. Thus, new protection solutions must be proposed to ensure circuit smooth operations not only for sub-critical functionalities but at the system architecture level itself.Based on these prerogatives, we present an innovative dynamical and distributed protection method, named D-Scale. This method consists in detecting, isolating and recovering the systems in the presence of error which lead to a "crash" of the platform. The crash error detection is based on heartbeat specific messages exchanged between PEs. The recovery phase is based on an autonomous mechanism which reconfigures the platform.A hardware/software implementation was proposed and evaluated. The protection cost is reduced in order to be integrated within future multi-processor SoC architectures. Finally, a fault effect analysis tool is studied in order to validate the fault-tolerant method robustness.

This master's thesis deals with the development of web portal for the application of fault-tolerant methodologies. It introduces the issue of fault-tolerant systems and analyze system requirements, that have users working in this field. It describes the development cycle from analysis and specification of application system design through to implementation and testing part. More thoroughly it is focusing above design portal that provides a comprehensive and versatile solution to the problem that leads to the final implementation of this portal. This realization is part of the thesis.

Submitted by Emanuel Varela Cardoso (emanuel.varela@ufcg.edu.br) on 2018-05-07T20:16:46Z No. of bitstreams: 1 ANTONIO ISAAC LUNA DE LACERDA – TESE (PPGEE) 2016.pdf: 20857733 bytes, checksum: 28767af2f770d3e0a8b3544e02207602 (MD5) / Made available in DSpace on 2018-05-07T20:16:46Z (GMT). No. of bitstreams: 1 ANTONIO ISAAC LUNA DE LACERDA – TESE (PPGEE) 2016.pdf: 20857733 bytes, checksum: 28767af2f770d3e0a8b3544e02207602 (MD5) Previous issue date: 2016-04-29 / A cont abilidade do equipamento de acionamento estático é extremamente importante do ponto de vista e ficiência energética. A detecção da falha é necessária para preservar o desempenho do conversor por um maior tempo possível. Este trabalho investiga a capacidade de tolerância a falhas do inversor e retifi cador ANPC (Active Neutral Point Clamped ) de três níveis modi ficado, quando suas chaves são submetidas a falhas de circuito aberto e curto circuito. Com o objetivo de melhorar o comportamento do conversor quando da falha de uma chave, foram introduzidos tiristores adicionais, um para cada chave do braço do inversor, e fusíveis em série com as chaves de grampeamento. São apresentados métodos para detecção e identi ficação de falhas juntamente com esquemas de reconfi gurações para trinta tipos de falhas. Resultados de simulação e experimentais corroboram os estudo teóricos de operação dos conversores. Os resultados de simulação são obtidos a partir do software PSIM, enquanto os resultados experimentais são obtidos a partir de uma plataforma de desenvolvimento experimental controlado pelo processador digital de sinais TMS320F28335. / The power electronics equipment reliability is a very important aspect from the energy e -ciency point of view. So, fault detection and its compensation, becomes extremely necessary for maintaining the process under fault condition near normal operation for a period of time as long as possible. This work investigates the fault-tolerant capacity of a modi ed three-level ANPC (Active Neutral Point Clamped) inverter and recti er when its switches are submitted to open and short-circuit failures. Additional thyristors, one for each inverter main switch, and fuses in series with the clamping switches have been introduced in order to improve the converter behavior when a switch fails. Fault detection and identi cation methods are presented together with con gured schemes for thirty types of failures. Simulation and experimental results are presented in order to con rm the validity of the proposed solutions, the simulation results are obtained from the software PSIM, whereas the experimental results are obtained from one experimental development platform controlled by a digital signal processor TMS320F28335.

In this Ph.D. thesis, a new methodology for the fault tolerant system state synchronization design and its recovery from faults is presented. A state synchronization method designed by means of the proposed methodology allows to repair the state of sequential logic elements implemented in the FPGA application logic, which cannot be repaired by the partial dynamic reconfiguration. The proposed methodology describes possible state synchronization design methods with respect to TMR granularity, dependence of the system function on its previous states and the system architecture. The methodology focuses on coarse-grained TMR architectures and state synchronization in the systems controlled by means of finite state machines or a processor. The use of the methodology is demonstrated on the CAN bus control system and the microcontroller NEO430, for which specific synchronization methods were designed. The systems reliability and new ability of the systems for recovery from faults were verified in the presence of simulated SEU faults. The experimental results and the contribution of this thesis are discussed in the conclusion.

<p>The advent of advanced communication technologies has given rise to large-scale networks comprised of numerous interconnected agents, which need to cooperate to accomplish various tasks, such as distributed message routing, formation control, robust statistical inference, and spectrum access coordination. These tasks can be formulated as distributed optimization problems, which require agents to agree on a parameter minimizing the average of their local cost functions by communicating only with their neighbors. However, distributed optimization algorithms are typically susceptible to malicious (or "Byzantine") agents that do not follow the algorithm. This thesis offers analysis and algorithms for such scenarios. As the malicious agent's function can be modeled as an unknown function with some fundamental properties, we begin in the first two parts by analyzing the region containing the potential minimizers of a sum of functions. Specifically, we explicitly characterize the boundary of this region for the sum of two unknown functions with certain properties. In the third part, we develop resilient algorithms that allow correctly functioning agents to converge to a region containing the true minimizer under the assumption of convex functions of each regular agent. Finally, we present a general algorithmic framework that includes most state-of-the-art resilient algorithms. Under the strongly convex assumption, we derive a geometric rate of convergence of all regular agents to a ball around the optimal solution (whose size we characterize) for some algorithms within the framework.</p>