Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-19T10:35:49Z (GMT). No. of bitstreams: 1 Santos_FilipedeAndradeTabarani_M.pdf: 11362655 bytes, checksum: 2e42c97ddd2bc2cb397c41f31568dc37 (MD5) Previous issue date: 2011 / Resumo: Este trabalho apresenta o estudo aprofundado e a confecção de amplificadores realimentados por corrente (CFA). São analisadas as principais características de um CFA e comparado com o amplificador realimentado por tensão (VOA). Buscou-se esclarecer as aplicações nas quais a primeira célula apresenta-se como melhor alternativa e como importante ferramenta a ser disponibiliza aos projetistas. Ao longo desta analise são frisadas as principais dificuldades na implementação da célula em tecnologia CMOS mencionando as soluções encontradas pela na literatura. Estas dificuldades impedem a confecção de CFAs CMOS comerciais. Um dos principais problemas da implementação de amplificadores realimentados por corrente em tecnologia CMOS e a baixa transcondutância dos transistores. A literatura propõe contornar esta deficiência da tecnologia utilizando células que obtêm alta transcondutância através do uso de realimentação interna [1]. Entretanto, a topologia proposta possui um severo compromisso entre transcondutância e banda de freqüência. O trabalho apresentado nesta dissertação deixa sua contribuição a literatura propondo dois métodos para amenizar este compromisso, que resultam no deslocamento da freqüência de -3dB, tornando-a significantemente maior que a original. No exemplo de projeto, aqui ilustrado, foi obtida banda 3,25 vezes a original,mantendo as características DC.O projeto de duas topologias, sendo uma baseada no primeiro CFA monolítico comercializado e a outra que utiliza transistores compostos, foi realizado visando a implementação monolítica em tecnologia 0,35 ?m CMOS da fabrica Austriamicrosystems. Os protótipos fabricados foram medidos e os resultados comparados com o esperado por simulação / Abstract: This work presents the study and design of current-feedback amplifiers (CFA).It is analyzed the main characteristics of a CFA as it compares to a typical voltage feedback amplifier (VOA). It was attempted to clarify in which applications the first mentioned cell excels at and why it can serve as an important tool for the designers. Throughout the analysis, the main difficulties regarding the implementation of the cell using CMOS technology are highlighted and the solutions proposed by the literature exposed. Those characteristics restrain the conception of CMOS commercials CFAs. One of the primary obstacles for the implementation of current-feedback amplifiers using CMOS technology is the low transconductance of the transistors. The literature proposes the use of cells with internal feedback in order to solve this issue [1].However, the proposed cell has a severe trade-off between transconductance and frequency bandwidth. This work provides its contribution to the literature by proposing two methods to loosen this trade-off. Using the proposed modification, it was obtained 3.25 times the original bandwidth while maintaining all of its native DC characteristics. The design of two topologies was carried out using monolithic Austriamicrosystems0.35?m CMOS technology; one based on the topology of the first commercialized monolithic CFA and the other using compound transistors. The produced prototypes were measured and the results compared with expected by simulation / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Microwave limiting amplifiers are the key components of Instantaneous Frequency Measurement (IFM) systems. Limiting amplifiers provide constant output power level in a wide input dynamic range and over a broad frequency band. Moreover, limiting amplifiers are high gain devices that are used to bring very low input power levels to a constant output power level. Besides, limiting amplifiers are required to provide minimum small signal gain ripple in order not to reduce the sensitivity of the IFM system over the operating frequency band. In this thesis work, a high gain, medium power, 2-18 GHz limiting amplifier module is designed, simulated, fabricated and measured. First, a 3-stage cascaded amplifier with 27 dB small signal gain is designed and fabricated. The 3-stage amplifier is composed of a novel cascaded combination of negative feedback and distributed amplifiers that provides the minimum small signal gain ripple and satisfactory input and output return losses inside 2-18 GHz frequency band. Then, the designed two 3-stage amplifiers and one 4-stage amplifier are cascaded to constitute a limiting amplifier module with minimum 80 dB small signal gain. The designed 10-stage limiting amplifier module also includes an analog voltage controllable attenuator to be used for compensating the gain variations resulting from temperature changes. The fabricated 10-stage limiting amplifier module provides 20 +/- 1.2 dBm output power level and excellent small signal gain flatness, +/- 2.2 dB, over 2-18 GHz frequency range.

Tato disertační práce pojednává o návrhu nových funkčních bloků použitelných v oblasti zpracování analogového signálu. Jde o obvody v proudové módu, které mohou ve vhodné konfiguraci pracovat v proudovém i v napěťovém módu. To umožnílo získat velmi nadějné výsledky v soustavách s nízkým napájecím napětím. Mnohostrannost těchto obvodů nalezne uplatnění v mnoha aplikacích. Zesilovač s proudovou zpětnou vazbou byl zavolen jako hlavní stavební blok pro detailní zkoumání funkce obvodů s RC operační sítí. Tato disertační práce pojednává o studiu, syntéze a návrhových aspektech realizace nových imitančních funkcí, jmenovitě induktivních a superkapacitních, proudových a napěťových konvejorech, kmitočtových filtrech s velkou jakostí, integrátorech a diferenciátorech, fázovacích členech s neminimální fází a napětím řízených oscilátorech. Disertační práce se detailně zabývá těmito novými bloky, které jsou popsány teoreticky a vyhodnoceny na základě simulací vlastností.

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.

This thesis deals with RC oscillators applicable in higher frequency ranges with the use of modern active elements. For individual function blocks (conveyor, current feedback amplifier, operational transconductance amplifier, voltage feedback amplifier) suitable models are suggested for the circuit simulator PSpice covering their characteristics on various levels, from an ideal one up to the full description of parasitic effects. On the basis of the study of recommended literature and company documentation various oscillator connections of the ranks 2 and 3 are suggested. By analysis through computer (PSpice, SNAP) the fulfilment of oscillation conditions, onset of oscillations were verified and by means of suitable simulations the effects of the impact on the parasitic characteristics of active elements was examined. Finally there are two oscillator connections stated and verified by simulations with the possibility of electronic retuning.

Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range. / <p>QC 20170905</p>