<p>Nonlinear systems occur in industrial processes, economical systems, biotechnology and in many other areas. The thesis treats methods for system identification and control of such nonlinear systems, and applies the proposed methods to a solar heating/cooling plant. </p><p>Two applications, an anaerobic digestion process and a domestic solar heating system are first used to illustrate properties of an existing nonlinear recursive prediction error identification algorithm. In both cases, the accuracy of the obtained nonlinear black-box models are comparable to the results of application specific grey-box models. Next a convergence analysis is performed, where conditions for convergence are formulated. The results, together with the examples, indicate the need of a method for providing initial parameters for the nonlinear prediction error algorithm. Such a method is then suggested and shown to increase the usefulness of the prediction error algorithm, significantly decreasing the risk for convergence to suboptimal minimum points. </p><p>Next, the thesis treats model based control of systems with input signal dependent time delays. The approach taken is to develop a controller for systems with constant time delays, and embed it by input signal dependent resampling; the resampling acting as an interface between the system and the controller.</p><p>Finally a solar collector field for combined cooling and heating of office buildings is used to illustrate the system identification and control strategies discussed earlier in the thesis, the control objective being to control the solar collector output temperature. The system has nonlinear dynamic behavior and large flow dependent time delays. The simulated evaluation using measured disturbances confirm that the controller works as intended. A significant reduction of the impact of variations in solar radiation on the collector outlet temperature is achieved, though the limited control range of the system itself prevents full exploitation of the proposed feedforward control. The methods and results contribute to a better utilization of solar power.</p>

<p>The presence of vibration is an important problem in many engineering applications. Various passive techniques have traditionally been used in order to reduce waves and vibrations, and their harmful effects. Passive techniques are, however, difficult to apply in the low frequency region. In addition, the use of passive techniques often involve adding mass to the system, which is undesirable in many applications.</p><p>As an alternative, active techniques can be used to manipulate system dynamics and to control the propagation of waves and vibrations. This thesis deals with modeling, estimation and active control of systems that have resonant dynamics. The systems are exposed to stochastic disturbances. Some of them excite the system and generate vibrational responses and other corrupt measured signals. </p><p>Feedback control of a beam with attached piezoelectrical elements is studied. A detailed modeling approach is described and system identification techniques are employed for model order reduction. Disturbance attenuation of a non-measured variable shows to be difficult. This issue is further analyzed and the problems are shown to depend on fundamental design limitations.</p><p>Feedforward control of traveling waves is also considered. A device with properties analogous to those of an electrical diode is introduced. An `ideal´ feedforward controller based on the mechanical properties of the system is derived. It has, however, poor noise rejection properties and it therefore needs to be modified. A number of feedforward controllers that treat the measurement noise in a statistically sound way are derived.</p><p>Separation of overlapping traveling waves is another topic under investigation. This operation also is sensitive to measurement noise. The problem is thoroughly analyzed and Kalman filtering techniques are employed to derive wave estimators with high statistical performance. </p><p>Finally, a nonlinear regression problem with close connections to unbalance estimation of rotating machinery is treated. Different estimation techniques are derived and analyzed with respect to their statistical accuracy. The estimators are evaluated using the example of separator balancing. </p>

The human central nervous system (CNS) contains a daunting number of cells and tremendous cellular diversity. A fundamental challenge of developmental neurobiology is to address the questions of how so many different types of neurons and glia can be generated at the precise time and place, making precisely the right connections. Resolving this issue involves dissecting the elaborate genetic networks that act within neurons and glia, as well as in the neural progenitor cells that generates them, to specify their identities. My PhD project has involved addressing a number of unresolved issues pertaining to how neural progenitor cells are specified to generate different types of neurons and glial cells in different temporal and spatial domains, and also how these early temporal and spatial cues are integrated to activate late cell fate determinants, which act in post-mitotic neural cells to activate distinct batteries of terminal differentiation genes. Analyzing the development of a specific Drosophila melanogaster (Drosophila) CNS stem cell – the neuroblast 5-6 (NB5-6) – we have identified several novel mechanisms of cell fate specification in the Drosophila CNS. We find that, within this lineage, the differential specification of a group of sequentially generated neurons – the Ap cluster neurons – is critically dependent upon the simultaneous triggering of two opposing feed-forward loops (FFLs) within the neuroblast. The first FFL involves cell fate determinants and progresses within the post-mitotic neurons to establish a highly specific combinatorial code of regulators, which activates a distinct battery of terminal differentiation genes. The second loop, which progresses in the neuroblast, involves temporal and sub-temporal genes that together oppose the progression of the first FFL. This leads to the establishment of an alternative code of regulators in late-born Ap cluster neurons, whereby alternative cell fates are specified. Furthermore, we find that the generation and specification of the Ap cluster neurons is modulated along the neuraxis by two different mechanisms. In abdominal segments, Hox genes of the Bithorax cluster integrates with Pbx/Meis factors to instruct NB5-6 to leave the cell cycle before the Ap cluster neurons are generated. In brain segments, Ap cluster neuron equivalents are generated, but improperly specified due to the absence of the proper Hox and temporal code. Additionally, in thoracic segments we find that the specification of the Ap cluster neurons is critically dependent upon the integration of the Hox, Pbx/Meis, and the temporal genes, in the activation of the critical cell fate determinant FFL. We speculate that the developmental principles of (i) feed-forward combinatorial coding; (ii) simultaneously triggered yet opposing feed-forward loops; and (iii) integration of different Hox, Pbx/Meis, and temporal factors, at different axial levels to control inter-segmental differences in lineage progression and specification; might be used widely throughout the animal kingdom to generate cell type diversity in the CNS.

Image recognition and -classification is becoming more important as the need to be able to process large amounts of images is becoming more common. The aim of this thesis is to compare two types of artificial neural networks, FeedForward Network and Convolutional Neural Network, to see how these compare when performing the task of image recognition. Six models of each type of neural network was created that differed in terms of width, depth and which activation function they used in order to learn. This enabled the experiment to also see if these parameters had any effect on the rate which a network learn and how the network design affected the validation accuracy of the models. The models were implemented using the API Keras, and trained and tested using the dataset CIFAR-10. The results showed that within the scope of this experiment the CNN models were always preferable as they achieved a statistically higher validation accuracy compared to their FFN counterparts.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.

More stringent requirements on nitrogen removal from wastewater are the motivation for this thesis. In order to improve treatment results and enhance cost-efficient operation of wastewater treatment plants, model based control strategies are presented. A Java based simulator for activated sludge processes (JASS) is presented. The graphical user interface, educational experiences and implemented control strategies are discussed. Controlling the addition of an external carbon source is the next topic discussed. A simple model based feedforward controller is derived and evaluated in a simulation study. The controller attenuates process disturbances quickly. Further, two feedforward controllers for adjusting the aeration volume in activated sludge processes are derived. The aim of the volume control strategies was to efficiently dampen the impact of process disturbances without using an excessively high dissolved oxygen concentration. The simulation results are promising and show that the aeration volume may be a feasible control variable. A linearisation method for static input non-linearities is presented. The method gives essentially the same result as the existing standard method, but possesses some implementational advantages. The method is used to linearise the non-linear oxygen transfer function of an activated sludge process in an application study. Multivariable interactions in a process model describing nitrate removal in an activated sludge process are studied using the well known RGA method as well as a relatively novel tool based on Hankel norms. The results of the analysis are compared to conclusions drawn from common process knowledge and are used to design a multivariable control strategy. It was found that process disturbances may be rejected faster using multivariable control. Finally, the operational costs of the denitrification process are investigated and visualised graphically. Cost optimal regions are found by a numerical grid search. Procedures for controlling the denitrification process in a cost-efficient way are described.

How can we evaluate and design integrated photonic circuit performance systematically? Can active photonic circuits be controlled for optimized performance? This work uses control theory to analyze, design, and optimize photonic integrated circuits based on versatile semiconductor optical amplifiers (SOAs). Control theory provides a mathematically robust set of tools for system analysis, design, and control. Although control theory is a rich and well-developed field, its application to the analysis and design of photonic circuits is not widespread. Following control theoretic methods already used for fibreline systems we derive three interrelated state-space models: a core photonic model, a photonic model with gain compression, and a equivalent circuit optoelectronic model. We validate each model and calibrate the gain compression model by pump/probe experiments. We then linearize the state-space models to design and analyze SOA controllers. We apply each linearized model to proof-of-concept SOA control applications such as suppressing interchannel crosstalk and regulating output power. We demonstrate the power of linearized state-space models in controller design and stability analysis. To illustrate the importance of using the complete equivalent circuit model in controller design, we demonstrate an intuitive bias-current controller that fails due to the dynamics of the intervening parasitic circuitry of the SOA. We use the linearized state-space models to map a relationship between feedback delay and controller strength for stable operation, and demonstrate that SOAs pose unusual control difficulties due to their ultrafast dynamics. Finally, we leverage the linearized models to design a novel and successful hybrid controller that uses one SOA to control another via feedback (for reliability) and feedforward (for speed) control. The feedback controller takes full advantage of the equivalent circuit modelling by sampling the voltage of the controlled SOA and using the error to drive the bias current of the controller SOA. Filtering in the feedback path is specified by transfer function analysis. The feedforward design uses a novel application of the linearized models to set the controller bias points correctly. The modelling and design framework we develop is entirely general and opens the way to the robust optoelectronic control of integrated photonic circuits.

This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.

How can we evaluate and design integrated photonic circuit performance systematically? Can active photonic circuits be controlled for optimized performance? This work uses control theory to analyze, design, and optimize photonic integrated circuits based on versatile semiconductor optical amplifiers (SOAs). Control theory provides a mathematically robust set of tools for system analysis, design, and control. Although control theory is a rich and well-developed field, its application to the analysis and design of photonic circuits is not widespread. Following control theoretic methods already used for fibreline systems we derive three interrelated state-space models: a core photonic model, a photonic model with gain compression, and a equivalent circuit optoelectronic model. We validate each model and calibrate the gain compression model by pump/probe experiments. We then linearize the state-space models to design and analyze SOA controllers. We apply each linearized model to proof-of-concept SOA control applications such as suppressing interchannel crosstalk and regulating output power. We demonstrate the power of linearized state-space models in controller design and stability analysis. To illustrate the importance of using the complete equivalent circuit model in controller design, we demonstrate an intuitive bias-current controller that fails due to the dynamics of the intervening parasitic circuitry of the SOA. We use the linearized state-space models to map a relationship between feedback delay and controller strength for stable operation, and demonstrate that SOAs pose unusual control difficulties due to their ultrafast dynamics. Finally, we leverage the linearized models to design a novel and successful hybrid controller that uses one SOA to control another via feedback (for reliability) and feedforward (for speed) control. The feedback controller takes full advantage of the equivalent circuit modelling by sampling the voltage of the controlled SOA and using the error to drive the bias current of the controller SOA. Filtering in the feedback path is specified by transfer function analysis. The feedforward design uses a novel application of the linearized models to set the controller bias points correctly. The modelling and design framework we develop is entirely general and opens the way to the robust optoelectronic control of integrated photonic circuits.

This thesis explores the clock and data recovery (CDR) for the high-speed blind-sampling ADC-based receivers. This exploration results in two new CDR architectures that reduce the receiver complexity and save the ADC power and area compared to the previous work. The two proposed CDR architectures constitute the primary contributions of this thesis. The first proposed architecture, a 2x feed-forward CDR architecture, eliminates the interpolating feedback loop, used in the previously reported CDRs, in order to reduce the CDR circuit complexity. Instead of the feedback loop, the proposed architecture uses a feed-forward topology to recover the phase and data directly from the blind digital samples of the received signal. The 2x feed-forward CDR architecture was implemented and characterized in a 5 Gb/s receiver test-chip in 65 nm CMOS. The test-chip measurements confirm that the CDR successfully recovers the data with bit error rate (BER) < 10e-12 in the presence of jitter. The second proposed architecture, a fractional-sampling-rate (FSR) CDR architecture, reduces the receiver sampling rate from the typical integer rate of 2x the baud rate to a fractional rate between 2x and 1x in order to reduce the ADC power and area. This architecture employs the feed-forward topology of the first contribution of this thesis to recover the phase and data from the fractionally-spaced digital samples of the signal. To verify the proposed FSR CDR architecture, a 1.45x receiver test-chip was implemented and characterized in 65 nm CMOS. This test-chip recovers 6.875 Gb/s data from the ADC samples taken at 10 GS/s. The measurements confirm a successful data recovery in the presence of jitter with BER < 10e-12. With sampling at 1.45x, the FSR CDR architecture reduces the ADC power and area by 27.3% compared to the 2x feed-forward CDR architecture, while the overall receiver power and area are reduced by 12.5%.