This thesis deals with design algorithms for filter banks based on optimization. The design specifications consist of the perfect reconstruction and frequency response specifications for finite impulse response (FIR) analysis and synthesis filters. The perfect reconstruction conditions are formulated as a set of linear equations with respect to the analysis filters’ coefficients and the synthesis filters’ coefficients. Five design algorithms are presented. The first three are based on an unconstrained optimization of performance indices, which include the perfect reconstruction error and the error in the frequency specifications. The last two algorithms are formulated as constrained optimization problems with the perfect reconstruction error as the performance index and the frequency specifications as constraints. The performance of the five algorithms is evaluated and compared using six examples; these examples include uniform filter bank, compatible non-uniform filter bank and incompatible non-uniform filter bank designs. The evaluation criteria are based on distortion and aliasing errors, the magnitude response characteristics of analysis and synthesis filters, the computation time required for the optimization, and the convergence of the performance index with respect to the number of iterations. The results show that the five algorithms can achieve almost perfect reconstruction and can meet the frequency response specifications at an acceptable level. In the case of incompatible non-uniform filter banks, the algorithms have challenges to achieve almost perfect reconstruction. / Graduate

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Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.

Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage.

Many emerging applications call for wideband analog-to-digital converters and some require medium-to-high resolution. Incorporating such ADCs allows for shifting as much of the signal processing tasks as possible to the digital domain, where more flexible and programmable circuits are available. However, realizing such ADCs with the existing single stage architectures is very challenging. Therefore, parallel ADC architectures such as time-interleaved structures are used. Unfortunately, such architectures require high-speed high-precision sample-and-hold (S/H) stages that are challenging to implement. In this thesis, a parallel ADC architecture, namely, the frequency-translating hybrid ADC (FTH-ADC) is proposed to increase the conversion speed of the ADCs, which is also suitable for applications requiring medium-to-high resolution ADCs. This architecture addresses the sampling problem by sampling on narrowband baseband subchannels, i.e., sampling is accomplished after splitting the wideband input signals into narrower subbands and frequency-translating them into baseband where identical narrowband baseband S/Hs can be used. Therefore, lower-speed, lower-precision S/Hs are required and single-chip CMOS implementation of the entire ADC is possible. A proof of concept board-level implementation of the FTH-ADC is used to analyze the effects of major analog non-idealities and errors. Error measurement and compensation methods are presented. Using four 8-bit, 100 MHz subband ADCs, four 25 MHz Butterworth filters, two 64-tap FIR reconstruction filters, and four 10-tap FIR compensation filters, a total system with an effective sample rate of 200 MHz is implemented with an effective number of bits of at least 7 bits over the entire 100 MHz input bandwidth. In addition, one path of an 8-GHz, 4-bit, FTH-ADC system, including a highly-linear mixer and a 5th-order, 1 GHz, Butterworth Gm-C filter, is implemented in a 90 nm CMOS technology. Followed by a 4-bit, 4-GHz subband ADC, the blocks consume a total power of 52 mW from a 1.2 V supply, and occupy an area of 0.05 mm2. The mixer-filter has a THD ≤ 5% (26 dB) over its full 1 GHz bandwidth and provides a signal with a voltage swing of 350 mVpp for the subsequent ADC stage. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Spectral efficiency is the key factor for the development of future wireless communications. Orthogonal Frequency Division Multiple Access (OFDMA) is the multiple access technology used at physical layer of latest wireless communication technologies. Anything on the improvement or overcoming the disadvantage of the present system will be considered for the future wireless systems. Long Term Evolution (LTE) is one of the 4th generation wireless communications and it is taken as the reference system in this thesis. The main concern of this thesis is to analyze the LTE radio frame. We designed and simulated the OFDM system with cyclic prefix, its Bit Error Rate (BER) is verified by changing the Signal to Noise Ratio (SNR) value and we investigated the OFDM system by eliminating the cyclic prefix. By eliminating cyclic prefix bandwidth efficiency is achieved, though using cyclic prefix in OFDM has more advantages. Filter banks are used to compensate the advantages of cyclic prefix when it is removed. Introducing Offset in QAM results in less distortion and amplitude fluctuations. We designed, simulated and compared the QAM digital modulation with Offset-QAM digital modulation its BER vs. SNR are verified using simulations on MATLAB.

Phased array receivers are a set of antenna elements that are capable of forming multiple simultaneous beams over a field of view. In radio astronomy, the study of deep space radio sources, a phased array feed (PAF) is placed at the focus of a large dish telescope that spatially samples the focal plane. PAFs provide an increase in the field of view as compared to the traditional single pixel horn feed, thereby increasing survey speed while maintaining low sensitivity. Phased arrays are also capable of radio frequency interference (RFI) mitigation which is useful in both radio astronomy and wireless communications when detecting signals in the presence of interferers such as satellites. Digital signal processing algorithms are used to process and analyze data provided by phased array receivers. During the commissioning of the Focal-plane L-band Array feed for the Green Bank telescope (FLAG), sensitivity consistent with an equivalent system temperature below 18 K was measured. To demonstrate the astronomical capability of the receiver, a pulsar (PSR B2011+38) was detected, and an HI source (NGC4258) was mapped with the real-time beamformer and fine channel correlator, respectively. This work also details improvements made to the software of the FLAG digital backend such as the design and implementation of an algorithm to remove scalloping ripple from the spectrum of two cascading polyphase filter banks (PFB). This work will also provide a brief introduction to a model-based beam interpolation algorithm capable of increasing spatial resolution of radio source maps as well as reducing time spent performing calibration. The development of a phased array receiver digital back end for the Office of Naval Research (ONR) is also detailed. This broadband system will be capable of communication in hostile RFI-rich environments with the aid of a real-time RFI mitigation algorithm currently implemented in software. This algorithm will be compatible with other PAF receiver systems and will enable RFI mitigation in other applications such as radio astronomy. This work will provide details on the implementation of this algorithm, the development and modification of other system software as well as full system tests of the 150 MHz bandwidth receiver have been conducted and will be shown in this document.

Phased array receivers are a set of antenna elements that are capable of forming multiple simultaneous beams over a field of view. In radio astronomy, the study of deep space radio sources, a phased array feed (PAF) is placed at the focus of a large dish telescope that spatially samples the focal plane. PAFs provide an increase in the field of view as compared to the traditional single pixel horn feed, thereby increasing survey speed while maintaining low sensitivity. Phased arrays are also capable of radio frequency interference (RFI) mitigation which is useful in both radio astronomy and wireless communications when detecting signals in the presence of interferers such as satellites. Digital signal processing algorithms are used to process and analyze data provided by phased array receivers. During the commissioning of the Focal-plane L-band Array feed for the Green Bank telescope (FLAG), sensitivity consistent with an equivalent system temperature below 18 K was measured. To demonstrate the astronomical capability of the receiver, a pulsar (PSR B2011+38) was detected, and an HI source (NGC4258) was mapped with the real-time beamformer and fine channel correlator, respectively. This work also details improvements made to the software of the FLAG digital backend such as the design and implementation of an algorithm to remove scalloping ripple from the spectrum of two cascading polyphase filter banks (PFB). This work will also provide a brief introduction to a model-based beam interpolation algorithm capable of increasing spatial resolution of radio source maps as well as reducing time spent performing calibration. The development of a phased array receiver digital back end for the Office of Naval Research (ONR) is also detailed. This broadband system will be capable of communication in hostile RFI-rich environments with the aid of a real-time RFI mitigation algorithm currently implemented in software. This algorithm will be compatible with other PAF receiver systems and will enable RFI mitigation in other applications such as radio astronomy. This work will provide details on the implementation of this algorithm, the development and modification of other system software as well as full system tests of the 150 MHz bandwidth receiver have been conducted and will be shown in this document.

No / Abstract: The scarcity of frequency spectrum used for wireless communication systems has attracted a considerable amount of attention in recent years. The cognitive radio (CR) terminology has been widely accepted as a smart platform mainly aimed at the efficient interrogation and utilization of permitted spectrum. Non-parametric spectrum sensing, or estimation, represents one of the prominent tools that can be proposed when CR works under an undetermined environment. As such, the periodogram, filter bank, and multi-taper methods are well considered in many studies without relying on the transmission channel's characteristics. A unified approach to all these non-parametric spectrum sensing techniques is presented in this paper with analytical and performance comparison using simulation methods. Results show that the multi-taper method outperforms the others.

This thesis studies the application of the wavelet filter bank (WFB) in perceptual audio coding by providing brief overviews of perceptual coding, psychoacoustics, wavelet theory, and existing wavelet coding algorithms. Furthermore, it describes the poor frequency localization property of the WFB and explores one filter design method, in particular, for improving channel separation between the wavelet bands. A wavelet audio coder has also been developed by the author to test the new filters. Preliminary tests indicate that the new filters provide some improvement over other wavelet filters when coding audio signals that are stationary-like and contain only a few harmonic components, and similar results for other types of audio signals that contain many spectral and temporal components. It has been found that the WFB provides a flexible decomposition scheme through the choice of the tree structure and basis filter, but at the cost of poor localization properties. This flexibility can be a benefit in the context of audio coding but the poor localization properties represent a drawback. Determining ways to fully utilize this flexibility, while minimizing the effects of poor time-frequency localization, is an area that is still very much open for research.