Flash Memories have been widely used as a storage media in electronic devices such as USB flash drives, mobile phones and cameras. Flash Memory offers a portable and non-volatile de- sign, which can be carried to everywhere without data loss. It is durable against temperature and humidity. With all these advantages, Flash Memory gets popular day by day. However, Flash Memory has also some disadvantages, such as erase-before restriction and erase limi- tation of each individual block. Erase-before restriction pushes every single writable unit to be erased before an update operation. Another limitation is that every block can be erased up to a fixed number. Flash Translation Layer - FTL is the solution for these disadvantages. Flash Translation Layer is a software module inside the Flash Memory working between the operating system and the memory. FTL tries to reduce these disadvantages of Flash Memory via implementing garbage collector, address mapping scheme, error correcting and many oth- ers. There are various Flash Translation Layer software. Some of them have been reviewed in terms of their advantages and disadvantages. The study aims at designing, implementing and simulating a NAND type FTL algorithm.

We are witnessing a proliferation of video in the Internet; YouTube is the most bandwidth intensive service of today’s Internet. It accounts for 20 - 35% of the Internet traffic with 35 hours of videos uploaded every minute and more than 700 billion playbacks in 2010. Netflix, a web service that streams premium contents such as TV series, shows, and movies, consumes 30% of the network bandwidth in North America at peak time. Recently, leveraging the content distribution networks (CDNs), a new paradigm for video streaming on the Internet has emerged, namely, Adaptive HTTP Streaming (AHS). AHS has become the industry standard for video streaming over the Internet adopted by broadcast networks as well as VoD services such as YouTube, Netflix, Hulu, etc. In the 90’s and early 2000’s, Internet-based video streaming for high-bitrate video was challenging due to hardware limitations. In that era, to cover the hardware limitations, every software component of a video server needed to be carefully optimized to support the real-time guarantees for jitter-free video delivery. However, most of the software solutions have become less important with the remarkable hardware improvements over the past two decades. There is 100× speedup in CPU speeds; RAM capacity has increased by 1,000×; hard disk drive (HDD) capacity has grown by 10,000×. Today, CPU is no longer a bottleneck for video streaming. On the other hand, storage bandwidth and network bandwidth are still serious bottlenecks for large scale on-demand video streaming. In this dissertation, we aim at a scalable video content distribution system that addresses both storage bottleneck and network bottleneck. The first part of the dissertation pertains to the storage system on the server side: A multi-tiered storage system that exploits a flash memory solid-state drive (SSD) can meet the bandwidth needs in a much more cost- effective way than a traditional two-tier storage system. We first identify the challenges in architecting such a system given the performance quirks of flash-based SSDs, and the lim- itations of state-of-the-art multi-tiered storage systems for video streaming. Armed with the knowledge of these challenges, we show how to construct such a storage system and implement a real web server with multi-tiered storage, evaluate the system with AHS work- loads, and demonstrate significant performance gains while reducing the TCO. The second part of the dissertation pertains to the network system on the client side: Integrating peer- to-peer (P2P) technology with the client-server paradigm results in a much more scalable video content distribution system. AHS is a paradigm for client-driven video streaming; its philosophy matches well with that of P2P video streaming. An adaptation mechanism is the most important component of AHS that determines overall video streaming quality and user experience. We show a throughput-smoothing-based adaptation mechanism that is designed for a client-server architecture does not work well for a P2P architecture. We pro- vide a buffer-based adaptation mechanism, evaluate our solution with OMNeT++/INET simulator, and demonstrate significant performance gains.

Dy-incorporated HfO₂ gate oxide with TaN gate electrode nMOS device has been developed for high performance CMOS applications in 22nm node technology. DyO /HfO bi-layer structure shows thin EOT with reduced leakage current and less charge trapping compared to HfO₂. Excellent electrical performance of the DyO-capped HfO₂ oxide n-MOSFET such as lower V[subscript TH], higher drive current, and improved channel electron mobility are reported. DyO/HfO samples also show better immunity for V[subscript TH] instability and less severe charge trapping characteristics. Its charge trapping characteristics, conduction mechanisms and dielectric reliability have been investigated in this work. As an application to memory device, HfON charge trapping layered NAND flash memory is developed and characterized. First, temperature-dependent Dy diffusion and the diffusion-driven Dy dipole formation process are discussed to clarify the origin of V[subscript TH] shift, and eventually modulate the effective work function in Dy-Hf-O/SiO₂ system. The Dy-induced dipoles are closely related to the Dy-silicate formation at the high-k/SiO₂ interfaces since the V[subscript FB] shift in Dy₂O₃ is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment, and becomes dominant in controlling the V[subscript FB]/V[scubscript TH] shift during high temperature annealing in the Dy- Hf-O/SiO₂ gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility. Second, to understand the reduced leakage current of the DyO/HfO sample, the effective barrier height of Dy₂O₃ was calculated from FN tunneling models, and the band diagram was estimated. The higher effective barrier height of Dy₂O₃, which is around 2.32 eV calculated from the F-N plot, accounts for the reduced leakage current in Dy incorporated HfO₂ nMOS devices. The lower barrier height of HfO₂ result in increased electron tunneling currents enhanced by the buildup of hole charges trapped in the oxide, which causes a severe increase of stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy incorporated HfO₂ inhibits a further increase of the electron tunneling from the TaN gate, and trapped holes lessen the hole tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO₂ dielectric demonstrates the high dielectric breakdown strength by weakening the charge trapping and defect generation during the stress. Based on these fundamental studies of the dielectric breakdown, modeling of time-dependent dielectric breakdown (TDDB) was done. The intrinsic TDDB of the Dy-doped HfO₂ gate oxide having 1 nm EOT is characterized by the progressive breakdown (PBD) model. At high temperature, the PBD becomes severe, since thermal energy causes carrier hopping between the localized weak spots. The voltage acceleration factor derived from the power law shows a realistic prediction in comparison with those from the 1/E model. The increase of the voltage acceleration factor at lower stress voltage is due to the lower trap generation rate in Dy- incorporated HfO₂. This voltage acceleration factor can be easily extended to include temperature dependency, and the effective activation energy derived from the power law is voltage dependent. Lastly, I studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al₂O₃/HfON/SiO₂/p-Si (TANOS) structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH₃ nitridation technique to incorporate nitrogen into the thin HfO₂ layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler-Nordheim (FN) tunneling current to increase the erase and programming speed. The trap-level energy in the HfON layer was calculated by using an amphoteric model. / text

abstract: Digital systems are essential to the technological advancements in space exploration. Microprocessor and flash memory are the essential parts of such a digital system. Space exploration requires a special class of radiation hardened microprocessors and flash memories, which are not functionally disrupted in the presence of radiation. The reference design ‘HERMES’ is a radiation-hardened microprocessor with performance comparable to commercially available designs. The reference design ‘eFlash’ is a prototype of soft-error hardened flash memory for configuring Xilinx FPGAs. These designs are manufactured using a foundry bulk CMOS 90-nm low standby power (LP) process. This thesis presents the post-silicon validation results of these designs. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

Depuis quelques années, les mémoires non-volatiles de type Flash sont présentes dans un grand nombre de systèmes sur puce. La grande densité d'intégration et la complexité de leur procédé de fabrication rendent les mémoires Flash de plus en plus sujette aux défauts. La présence de défauts dans les mémoires est une des problématiques majeures. En effet, de tels défauts pourraient affecter le rendement, la rétention, l'endurance et donc la fiabilité des mémoires Flash. Cette thèse a porté sur l'analyse des mécanismes de défaillances, la modélisation des comportements fautifs et le développement de solution en vue d'améliorer le test des mémoires Flash. Dans ce contexte, nous avons proposé un modèle SPICE de la mémoire Flash TSTAC™ d'ATMEL. En comparaison avec l'état de l'art, le modèle SPICE proposé permet de simuler les opérations fonctionnelles de la mémoire de manière dynamique. Ce modèle a était utilisé pour effectuer des simulations d'injections de défauts réalistes pouvant affecter la matrice de la mémoire Flash TSTAC™. Ces simulations ont permis de prédire leurs comportements fautifs et de déterminer leurs modèles de fautes. D'autres types de simulations électriques effectuées à l'aide du modèle électrique ont permis de développer deux méthodes de caractérisation : la première permettant de détecter les variations d'épaisseur d'oxyde des cellules mémoires ; la deuxième méthode permet de caractériser la programmation par pulsation (pulse programming) et ainsi prédire la valeur du champ électrique durant l'écriture d'une cellule. / In recent years, non-volatile Flash memories have been widely used on system on chip. Their high integration density and complexity of manufacturing process make the Flash memory prone to defects. The defects in the memory are one of the major issues. They could affect the performance, retention, endurance, and therefore the reliability of Flash memories. This thesis was focused on the analysis of failure mechanisms, the faulty behavior modeling and the development of solution in order to improve the testing of Flash memories. In this work, we have proposed an electrical SPICE model of an ATMEL Flash memory. Compared with the state of art, the proposed model allows to simulate the static and dynamic behavior of the memory. This model is used to perform defect injection simulations affecting the Flash memories. These simulations are able to predict faulty behavior by fault modeling. Other types of electrical simulations highlight two characterization methods. The first one is able to detect the oxide thickness variations of the memory cells; the second one allows to characterize the programming pulse and then predict the electric field value during the programming of the cell.

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