Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, variational delay evaluation and path selection under process variation. Previous research of fault modeling on resistive spot defects, such as resistive opens and bridges in the interconnect, and resistive shorts in devices, lacked an accurate fault model. As a result it was difficult to perform fault simulation and select the best vectors. Conventional methods to compute variational delay under process variation are either slow or inaccurate. On the problem of path selection under process variation, previous approaches either choose too many paths, or missed the path that is necessary to be tested. We present new solutions in this dissertation. A new fault model that clearly and comprehensively expresses the relationship between electrical behaviors and resistive spots is proposed. Then the effect of process variations on path delays is modeled with a linear function and a fast method to compute coefficients of the linear function is also derived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test while the fault coverage is satisfied. The experimental results show that the new solutions are efficient and accurate.

No description available.

Depuis quelques années, les mémoires non-volatiles de type Flash sont présentes dans un grand nombre de systèmes sur puce. La grande densité d'intégration et la complexité de leur procédé de fabrication rendent les mémoires Flash de plus en plus sujette aux défauts. La présence de défauts dans les mémoires est une des problématiques majeures. En effet, de tels défauts pourraient affecter le rendement, la rétention, l'endurance et donc la fiabilité des mémoires Flash. Cette thèse a porté sur l'analyse des mécanismes de défaillances, la modélisation des comportements fautifs et le développement de solution en vue d'améliorer le test des mémoires Flash. Dans ce contexte, nous avons proposé un modèle SPICE de la mémoire Flash TSTAC™ d'ATMEL. En comparaison avec l'état de l'art, le modèle SPICE proposé permet de simuler les opérations fonctionnelles de la mémoire de manière dynamique. Ce modèle a était utilisé pour effectuer des simulations d'injections de défauts réalistes pouvant affecter la matrice de la mémoire Flash TSTAC™. Ces simulations ont permis de prédire leurs comportements fautifs et de déterminer leurs modèles de fautes. D'autres types de simulations électriques effectuées à l'aide du modèle électrique ont permis de développer deux méthodes de caractérisation : la première permettant de détecter les variations d'épaisseur d'oxyde des cellules mémoires ; la deuxième méthode permet de caractériser la programmation par pulsation (pulse programming) et ainsi prédire la valeur du champ électrique durant l'écriture d'une cellule. / In recent years, non-volatile Flash memories have been widely used on system on chip. Their high integration density and complexity of manufacturing process make the Flash memory prone to defects. The defects in the memory are one of the major issues. They could affect the performance, retention, endurance, and therefore the reliability of Flash memories. This thesis was focused on the analysis of failure mechanisms, the faulty behavior modeling and the development of solution in order to improve the testing of Flash memories. In this work, we have proposed an electrical SPICE model of an ATMEL Flash memory. Compared with the state of art, the proposed model allows to simulate the static and dynamic behavior of the memory. This model is used to perform defect injection simulations affecting the Flash memories. These simulations are able to predict faulty behavior by fault modeling. Other types of electrical simulations highlight two characterization methods. The first one is able to detect the oxide thickness variations of the memory cells; the second one allows to characterize the programming pulse and then predict the electric field value during the programming of the cell.

No description available.

L'état de contrainte initial est l'état de contrainte dans le sous-sol avant toute intervention humaine. Sa connaissance est essentielle pour atteindre des objectifs aussi bien scientifiques (compréhension de la tectonique des plaques) que préventifs (étude et prédiction des séismes) ou industriels (compréhension de la mécanique des réservoirs pétroliers pour leur exploitation). Dans cette thèse, nous présentons une méthode permettant d'estimer l'état de contrainte initial en trois dimensions, à partir de données éparses. Cette méthode repose sur une approche inverse dans laquelle la méthode des éléments finis est utilisée pour résoudre le problème mécanique élastique. Les paramètres de modèles sont les conditions de Neumann décrites par des fonctions linéaires par morceaux. Les données sont des mesures partielles de l'état de contrainte en quelques points du domaine d'étude. Une optimisation d'ensemble est utilisée pour résoudre le problème inverse. La méthode est testée sur un cas synthétique où la solution de référence dans tout le domaine est supposée connue. Sur cet exemple, la méthode présentée est capable de retrouver un état de contrainte en accord avec les mesures, et cohérent avec l'état de contrainte de référence dans tout le domaine. La méthode est ensuite enrichie par des critères mécaniques qui contraignent l'état de contrainte dans les zones où les données sont absentes. La méthode est ensuite appliquée sur un cas réel: le bassin de Neuquèn en Argentine, sur lequel des données de puits sont disponibles. La confrontation de la méthode avec un cas d'étude permet de déterminer quelles en sont les limites. L'impact des failles sur l'état de contrainte et les différentes façons de les modéliser sont discutés. En effet, la prise en compte de ces structures complexes est problématique dans les calculs induits par les méthodes inverses puisqu'elles introduisent des non linéarités rendant le temps de calcul trop important. Nous investiguons alors la possibilité de les modéliser uniquement par des propriétés élastiques. Enfin, nous consacrons un chapitre sur l'environnement logiciel intégratif que nous avons développé pour la réalisation des calculs mécaniques. Cet environnement est composé de RINGMesh, une bibliothèque proposant une structure de données pour les modèles géologiques et de RINGMecha, permettant la réalisation de calculs mécaniques sur ces modèles. RINGMecha interface plusieurs simulateurs, chacun ayant ses spécificités, de manière totalement transparente pour l'utilisateur. RINGMecha a été utilisé pour la réalisation de tous les calculs présentés dans cette thèse et a été pensé pour pouvoir être étendu à d'autres problèmes, avec d'autres simulateurs / Initial stress state is the stress state before any human activity. Its knowledge is essential when dealing with scientific (understanding of plate tectonics), preventive (earthquake prediction) and industrial (understanding reservoirs before their exploitation) purposes. We present a method to estimate the initial stress state in a 3D domain from sparse data. This method relies on an inverse approach which uses the finite elements method to solve the elastic mechanical problem. The model parameters are Neumann conditions, which are defined as piecewise linear functions. The data parameters are stress state observations, such as intensity and orientation at a few points. An ensemble optimization method is used to solve the inverse problem. The method is tested on a synthetic case where the reference solution is known. On this example, the method succeeds in retrieving the stress state at data points as well as in the whole domain. The method is enriched with a mechanical criterion which imposes mechanical constraints in the domain under study. The method is then applied to a real case: the Neuquèn basin in Argentina where borehole stress data is available. This application reveals some of the limits of the presented method. Then, the effect of faults on the stress state is investigated. Different modeling strategies are presented: the objective is to reduce the computing cost, which can be very high when dealing with such complex structures. We propose to model them using only elastic properties. Finally, we present the integrative software which were developed to run mechanical simulations. RINGMesh handles the structural model data structure and RINGMecha runs the mechanical simulations on the model. RINGMecha is interfaced with several simulators. Each of them can be called separately, depending on the problem to be solved. The interface of RINGMecha with third party simulators is done in a user friendly manner. RINGMecha was used for all the computations presented in this thesis. It was built in order to be extended to other problems, with other simulators

Modeling, fault assessment, and diagnostics of rolling element bearings and induction motors were studied. Dynamic model of rolling element bearings with faults were developed using vector bond graphs. The model incorporates gyroscopic and centrifugal effects, contact deflections and forces, contact slip and separations, and localized faults. Dents and pits on inner race, outer race and balls were modeled through surface profile changes. Experiments with healthy and faulty bearings validated the model. Bearing load zones under various radial loads and clearances were simulated. The model was used to study dynamics of faulty bearings. Effects of type, size and shape of faults on the vibration response and on dynamics of contacts in presence of localized faults were studied. A signal processing algorithm, called feature plot, based on variable window averaging and time feature extraction was proposed for diagnostics of rolling element bearings. Conducting experiments, faults such as dents, pits, and rough surfaces on inner race, balls, and outer race were detected and isolated using the feature plot technique. Time features such as shape factor, skewness, Kurtosis, peak value, crest factor, impulse factor and mean absolute deviation were used in feature plots. Performance of feature plots in bearing fault detection when finite numbers of samples are available was shown. Results suggest that the feature plot technique can detect and isolate localized faults and rough surface defects in rolling element bearings. The proposed diagnostic algorithm has the potential for other applications such as gearbox. A model-based diagnostic framework consisting of modeling, non-linear observability analysis, and parameter tuning was developed for three-phase induction motors. A bond graph model was developed and verified with experiments. Nonlinear observability based on Lie derivatives identified the most observable configuration of sensors and parameters. Continuous-discrete Extended Kalman Filter (EKF) technique was used for parameter tuning to detect stator and rotor faults, bearing friction, and mechanical loads from currents and speed signals. A dynamic process noise technique based on the validation index was implemented for EKF. Complex step Jacobian technique improved computational performance of EKF and observability analysis. Results suggest that motor faults, bearing rotational friction, and mechanical load of induction motors can be detected using model-based diagnostics as long as the configuration of sensors and parameters is observable. / text

A vast expansion is found in the field of automotive electronic systems. The expansion iscoupled with a related increase in the demands of power and design. Now, this is goodarena of engineering opportunities and challenges. One of the challenges faced, isdeveloping fault tolerant systems, which increases the overall automotive and passengersafety. The development in the field of automotive electronics has led to the innovationof some very sophisticated technology. However, with increasing sophistication intechnology also rises the requirement to develop fault tolerant solutions.As one of many steps towards developing a fault tolerant system, this thesis presents anexhaustive fault analysis. The modeling and fault analysis is carried out for a vehicle withfour in-wheel motors. The primary goal is to collect as many of the possible failuremodes that could occur in a vehicle. A database of possible failure modes is retrievedfrom the Vehicle Dynamics research group at KTH. Now with further inputs to thisdatabase the individual faults are factored with respect to change in parameters of vehicleperformance. The factored faults are grouped with respect to similar outputcharacterization.The fault groups are modeled and integrated into a vehicle model developed earlier inMatlab/Simulink. All the fault groups are simulated under specific conditions and theresults are obtained. The dynamic behavior of the vehicle under such fault conditions isanalyzed. Further, in particular the behavior of the vehicle with electronic stabilitycontrol (ESC) under the fault conditions is tested. The deviation in the vital vehicleperformance parameters from nominal is computed.Finally based on the results obtained, a ranking system termed Severity Ranking System(SeRS) is presented. The severity ranking is presented based on three essential vehicleperformance parameters, such as longitudinal acceleration ( ), lateral acceleration ( )and yaw rate ( ̇ ). The ranking of the faults are classified as low severity S1, mediumseverity S2, high severity S3 and very high severity S4. A fault tolerant system must beable to successfully detect the fault condition, isolate the fault and provide correctiveaction. Hence, this database would serve as an effective input in developing fault tolerantsystems.

A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross section for specific FPGA designs. The results of this radiation testing were then analyzed and compared with similar fault injection tests, with results suggesting that the fault injection tool behavior is indeed accurate and valid. The fault injection tool can be used to determine the sensitivity of an FPGA design to configuration memory upsets. Additionally, fault mitigation techniques designed to increase the reliability of an FPGA design in spite of upsets within the configuration memory, can be thoroughly tested through fault injection. Fault injection testing should help to increase the feasibility of reconfigurable computing in space. FPGAs are well suited to the computational demands of space based signal processing applications; however, without appropriate mitigation or redundancy techniques, FPGAs are unreliable in a radiation environment. Because the fault injection tool has been shown to reliably model the effects of single event upsets within the configuration memory, it can be used to accurately evaluate the effectiveness of fault tolerance techniques in FPGAs.

No description available.

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.