ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / The desire to control an LRU and/or MIL-STD 1760 store via an independent 1553 stream on current weapon platforms created the need for the development of the BCT-302 1553 Test Bus Card. This solution solves the issues of integration without the need to perform an aircraft OFP change. The BCT- 302 is a customized MIL-STD-1553 card for use in Teletronics Technology Corporation, (TTC), Airborne Instrumentation Multiplexer (AIM) and High-Speed Avionics Data Acquisition Unit (HSAVDAU) products. The BCT-302 card consists of two redundant MIL-STD-1553 ports. Each port is independently configurable by the AIM/HSAVDAU host processor to function as a Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM). The system is capable of cherry picking parameters from any 1553 bus and retransmitting assembled messages to a weapon and/or an LRU in a 1553 format. This paper describes the design requirements of the BCT card and how those requirements were met during an AIM-9X launch on an F-22.

In modern embedded systems, real-time applications are often executed on multi-core systems that also run non real-time critical applications. It is well known that cache sharing among multi-core systems or concurrent threads running on a single CPU potentially causes real-time application execution delays. This makes the worst-case execution time (WCET) prediction of these real-time applications more difficult. An encouraging approach to address this problem is prioritized cache. Currently, the implementation of prioritized cache is done at the architectural level using cache controllers. This thesis focuses on the implementation of two prioritized LRU (least-recently-used) cache replacement policy circuits inside the cache circuit to support the prioritized cache operation. This will decrease cache latency. The circuits are implemented using the Synopsys 28nm EDK. Based on the circuit implementation, the area and power overheads associated with prioritized cache are investigated. Two prioritized LRU circuit designs are presented.

Aujourd'hui, la notion de gestion a été remplacée par celle de leadership. Le leadership et ses impacts sur la performance de l'organisation ont été étudiés par de nombreux chercheurs. Cependant, peu d’études ont porté sur le leadership efficace dans les universités en tant que type d'organisation. L'enseignement supérieur français a récemment connu une réforme importante (LRU). Les débats sur ses aspects positifs et négatifs ont été vifs et le sont encore. Dans le cadre de cette réforme, le leadership semble avoir plus d'importance, dans la mesure où une plus grande autonomie voire plus de pouvoir formel ont été délégués aux présidents d'université. Dans notre recherche, nous avons étudié les comportements de leadership efficace chez les présidents d'universités françaises, et nous les avons comparés avec les mêmes comportements chez les présidents d'universités Iraniennes. Prenant en compte des facteurs sociaux, culturels et politiques, ces comparaisons donnent des résultats intéressants. Pour nos recherches, nous avons utilisé la théorie du leadership de Kouzes et Posner (2003), qui ont identifié cinq comportements de leadership efficace (Model the way, Inspire a shared vision, Challeng the process, Enable others to act, Encourage the heart) et développé des questionnaires d’Inventaires de Pratiques de Leadership (Leadership Practices Inventaire, LPI) à partir de visions croisés (Questionnaires «Soi » et «autres»). L'objectif principal est d'évaluer dans quelle mesure les présidents d'université français et iraniens sont impliqués dans ces comportements. Les questionnaires LPI, ainsi que huit questions ouvertes, ont été soumis à tous les présidents d'universités publiques en Iran et en France, et à cinq vice-présidents de chaque université. Nous avons reçu un total de 107 réponses sur la France et 72 réponses en l'Iran. Les résultats ont été analysés en utilisant SPSS 11.5, et une analyse de contenu a été réalisée pour des questions ouvertes. Les réponses des vice-présidents montrent que les présidents d'université français présentent des scores plus élevés dans tous les comportements de leadership efficace par rapport aux présidents Iraniens. En outre, sur la base des réponses des présidents eux-mêmes, les présidents français ont score plus élevé sur quatre comportements, tandis que les présidents Iraniens s’estiment plus impliqués dans le comportement « mettre en question les processus » (Challenging the process). Toutefois, les scores des deux pays sont faibles en comparaison des scores globaux moyens aux LPI pour les dirigeants d'autres pays, y compris des dirigeants nord-américains. Les interprétations possibles de cette différence sont discutées en détail. / Nowadays the notion of management has been replaced by leadership. Leadership and its impacts on organization performance have been studied by many researchers. However, not many studies have focused on effective leadership in universities as a kind of organization. French higher education underwent a substantial reform recently (LRU). And there is still much debate about its positive and negative aspects. In light of these reforms, leadership seems to gain more importance, as more autonomy and power is delegated to the university presidents. In this research, we study effective leadership behaviors among French university presidents, and compare them with the same behaviors among Iranian university presidents. Considering different social, cultural and political background, comparison of two countries would yield interesting results.For our research, we used Kouzes and Posner’s theory of leadership (2003), who identified five effective leadership behaviors (Model the way, Inspire a shared vision, Challeng the process, Enable others to act, and Encourage the heart) and developed Leadership Practices Inventory (LPI) questionnaire (‘Self’ and ‘Others’ versions). The main objective is to evaluate to what extent French and Iranian university presidents are engaged in these behaviors. LPI, as well as eight open-ended questions, were submitted to all public university presidents in Iran and France, and five vice presidents in each university. We received a total of 107 responses from France and 72 responses from Iran. The results were analyzed using SPSS 11.5, and content analysis was performed for open-ended questions. The results show that, according to vice presidents opinion, the French university presidents had higher scores in all effective leadership behaviors compared to Iranian presidents. Also, based on the presidents’ opinion, French presidents had higher score in four behaviors, while Iranian presidents were more involved in ‘Challenging the process’ behavior. However, scores from both countries were lagging behind, compare to overall average score received by other leaders filing this questionnaire, including North American leaders. Possible reasons for this difference are discussed in detail.

The importance of a smooth user experience in applications is increasing. To achieve more performance when interacting with resource intensive data it is important to implement an efficient caching method. The goal of this thesis is to investigate how to implement an efficient cache in an Android application. The use case is to download metadata and images of movies from a WebAPI provided by June AB. In order to investigate which caching method is the most efficient, a pre-study was done on some of the most common caching methods today. Based on the results of the pre-study, two different caching algorithms were tested and evaluated: First-In First-Out (FIFO) and Least Recently Used (LRU). These two algorithms were then implemented in an Android application. The resulting prototype has a responsive user interface capable of caching large amounts of data without noticeable performance loss compared to a non-cached version. The results from the prototype showed that LRU is the better strategy in our use case, however what we discovered was that the buffer size of the cache has the biggest impact on performance, not the cache eviction strategy. / Vikten av en snabb användarupplevelse ökar i nya applikationer. För att få ut mer prestanda när användare interagerar med resurstung data är det viktigt att implementera en effektiv cachingsmetod. Målet med arbetet är att undersöka hur man implementerar en effektiv cache i en Android-applikation. Användarfallet är att ladda ner metadata och bilder på filmer från ett WebAPI som tillhandahölls av June AB. För att undersöka vilken cachingsmetod som är effektivast gjordes en förstudie på några av de mest vanliga cachingsmetoderna idag. Baserat på förstudiens resultat valdes två cachingsalgoritmer för testning och utvärdering: First-In First-Out (FIFO) och Least Recently Used (LRU). Dessa två algoritmer implementerades i en Android-applikation Prototypen som gjordes har ett responsivt användargränsnitt som kan cacha stora mängder data utan märkbar prestandaförlust jämfört med en icke-cachad version. Prototypen visade att LRU är den bättre strategin för vårt användarfall, men upptäckte att bufferstorleken på cachen har den största påverkan av prestandan, inte cachestrategin.

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With the advancement of technology, multi-cores with shared cache have been used in real-time applications. In such systems, some cores run real-time applications and some cores run other non-critical applications that do not have strict deadline. Due to the sharing of cache by multi-core processors, problems predicting the actual execution time and the execution time of real-time applications have emerged. To address these problems, cache memory with prioritized replacement policy is proposed. Most of the work is carried out in high-level hardware designs and software based application level designs. No low-level hardware implementations of cache memory with prioritized replacement circuits have been designed to the best of my knowledge. My thesis focuses on designing a LRU replacement circuit that is prioritized based on the application the processor is running. Real-time applications acquire priority in using the cache memory over other applications which enhance the seamless execution of the real-time application and hence supports execution time predictability which in turn helps improve the potential of multi-core computing of real-time systems. The speed, size and power overhead are analyzed by placing the N-way set associative LRU as a part of cache of size 128KB designed using 65nm CMOS technology.

Este trabalho apresenta um estudo sobre o problema de substituição de linhas de cache em microprocessadores. Inspirado no conceito de Entropia da Informação proposto em 1948 por Claude E. Shannon, este trabalho propõe uma nova heurística de substituição de linhas de cache. Seu objetivo é capturar e explorar melhor a localidade de referência dos programas e diminuir a taxa de miss rate durante a execução dos programas. O algoritmo proposto, Entropy, utiliza a heurística de entropia da informação para estimar as chances de uma linha ou bloco de cache ser referenciado após ter sido carregado na cache. Uma nova função de decaimento de entropia foi introduzida no algoritmo, otimizando seu funcionamento. Dentre os resultados obtidos, o Entropy conseguiu reduzir em até 50,41% o miss rate em relação ao algoritmo LRU. O trabalho propõe, ainda, uma implementação em hardware com complexidade e custo computacional comparáveis aos do algoritmo LRU. Para uma memória cache de segundo nível com 2-Mbytes e 8-way associative, a área adicional requerida é da ordem de 0,61% de bits adicionais. O algoritmo proposto foi simulado no SimpleScalar e comparado com o algoritmo LRU utilizando-se os benchmarks SPEC CPU2000. / This work presents a study about cache line replacement problem for microprocessors. Inspired in the Information Entropy concept stated by Claude E. Shannon in 1948, this work proposes a novel heuristic to replace cache lines in microprocessors. The major goal is to capture the referential locality of programs and to reduce the miss rate for cache access during programs execution. The proposed algorithm, Entropy, employs that new entropy heuristic to estimate the chances of a cache line to be referenced after it has been loaded into cache. A novel decay function has been introduced to optimize its operation. Results show that Entropy could reduce miss rate up to 50.41% in comparison to LRU. This work also proposes a hardware implementation which keeps computation and complexity costs comparable to the most employed algorithm, LRU. To a 2-Mbytes and 8-way associative cache memory, the required storage area is 0.61% of the cache size. The Entropy algorithm was simulated using SimpleScalar ISA simulator and compared to LRU using SPEC CPU2000 benchmark programs.

Este trabalho apresenta um estudo sobre o problema de substituição de linhas de cache em microprocessadores. Inspirado no conceito de Entropia da Informação proposto em 1948 por Claude E. Shannon, este trabalho propõe uma nova heurística de substituição de linhas de cache. Seu objetivo é capturar e explorar melhor a localidade de referência dos programas e diminuir a taxa de miss rate durante a execução dos programas. O algoritmo proposto, Entropy, utiliza a heurística de entropia da informação para estimar as chances de uma linha ou bloco de cache ser referenciado após ter sido carregado na cache. Uma nova função de decaimento de entropia foi introduzida no algoritmo, otimizando seu funcionamento. Dentre os resultados obtidos, o Entropy conseguiu reduzir em até 50,41% o miss rate em relação ao algoritmo LRU. O trabalho propõe, ainda, uma implementação em hardware com complexidade e custo computacional comparáveis aos do algoritmo LRU. Para uma memória cache de segundo nível com 2-Mbytes e 8-way associative, a área adicional requerida é da ordem de 0,61% de bits adicionais. O algoritmo proposto foi simulado no SimpleScalar e comparado com o algoritmo LRU utilizando-se os benchmarks SPEC CPU2000. / This work presents a study about cache line replacement problem for microprocessors. Inspired in the Information Entropy concept stated by Claude E. Shannon in 1948, this work proposes a novel heuristic to replace cache lines in microprocessors. The major goal is to capture the referential locality of programs and to reduce the miss rate for cache access during programs execution. The proposed algorithm, Entropy, employs that new entropy heuristic to estimate the chances of a cache line to be referenced after it has been loaded into cache. A novel decay function has been introduced to optimize its operation. Results show that Entropy could reduce miss rate up to 50.41% in comparison to LRU. This work also proposes a hardware implementation which keeps computation and complexity costs comparable to the most employed algorithm, LRU. To a 2-Mbytes and 8-way associative cache memory, the required storage area is 0.61% of the cache size. The Entropy algorithm was simulated using SimpleScalar ISA simulator and compared to LRU using SPEC CPU2000 benchmark programs.

O desempenho do sistema de memória virtual depende diretamente da qualidade da política de gerência de memória. Estratégias podem ser desenvolvidas para melhorar tal desempenho: uma delas é criar novas políticas de gerência de memória que tenham, ao mesmo tempo, bom desempenho e simplicidade; outra maneira é desenvolver técnicas e incluir informações para auxiliar as políticas já existentes. Este trabalho procura mostrar uma estratégia para auxiliar políticas de substituição com a finalidade de obter bom desempenho em um sistema de gerência de memória, sem a necessidade de alterar o comportamento da política de substituição. Para isso, foi utilizada a técnica de busca antecipada de páginas em conjunto com a informação de frequência de acessos, obtida por meio de um método usado em processamento estatístico de linguagem natural. Os resultados mostram, além do bom desempenho, que a mesma estratégia pode ser adotada em qualquer algoritmo. / The virtual memory system performance depends directly on the quality of the memory management policy. Strategies can be developed to improve such performance: one of them is creating new memory management policies that present, at the same time, simplicity and good performance; another one is developing techniques and include information that will aid the policies that already exist. This paper aims to show a strategy that will aid replacement policies in order to obtain a good performance in a memory management system without changing the replacement policy behavior. To do so, a page prefetching technique along with information about access frequency, obtained through a method used in a statistical natural language processing, was used. The results show, besides the good performance, that the same strategy can be adopted in any algorithm.

Controlling the authenticity of a product in the supply chain has been a struggle formanufacturers, and increasing complexity of the chains intensifies the imitation andcounterfeiting threats. Indeed, counterfeiting is absent from effective control in supply chainand manufacturers are looking for a technology to supply this control. The ability of RFID toprovide a tagged item with unique electronic code, it’s characteristic to hold some historicaldata about the item and supply automatic, immediate and accurate data about the tagged itemattracts manufacturers to use RFID technology to provide the effective control throughout thesupply chain. In line with this issue, SToP1 (Stop Tampering of Products), an EU foundedproject, aimed at developing an anti-counterfeiting solution based on auto-identificationtechnologies for consortium companies concerned with or affected by fake products. SToP iscommitted to establish the business cases, do research and at the end issue applicationguidelines for using RFID technology against counterfeiting in particular business contexts.Under SToP’s umbrella, this master thesis is initiated with the purpose to design a practicalguideline for choosing an appropriate RFID system for anti-counterfeiting in the aviationindustry that is one of the affected industries.The conclusion of the thesis consists of a number of sections, which altogether fulfill thepurpose of the thesis. The thesis forms a base for continues challenge of implementing RFIDas an anti-counterfeiting device focusing on the aviation industry, proposes solution scenariosbased on RFID technology, suggests applicable standards and proposes a secure RFID methodto prevent counterfeiting specially in the aviation industry. Jointly, these sections fromguidelines as a foundation for decision-making for kind of RFID system for anti-counterfeitingapplication in the aviation industry. / Uppsatsnivå: D