A time-independent finite-difference numerical scheme is developed to study the dynamic responses of both submerged , floating breakwater and composite floating breakwaters under wave force . The composite floating breakwaters is based on a moored floating bodies and submerged obstacle. The fully nonlinear kinematic free surface conditions and dynamic conditions are considered in the analysis .The numerical results were validated by several bench mark studies and existing reporting results. The wave reducing effect of both submerged, floating breakwaters and composite floating breakwaters were analysis and discussed¡C

Abstract A boundary element method numerical scheme is developed to study the dynamic response and the wave damping characteristics of a floating structure under an incident wave approaching. The coupled surge, heave and pitch motion of a floating structure are included in the model. The equation of motion of the numerical model has been set up; meanwhile the solution of equations has been solved through the Runge-Kutta fifth order method. The hydrodynamic physical model tests have been carried out to verify the goodness of the numerical model. The numerical solutions and the experimental results have good agreements. It means that the BEM developed by this paper has its own accuracy. The study results show that the wave with shorter period has better effect on wave damping. In general, a floating breakwater, which is deeper under the water and wider in width, has smaller transmission coefficients. Practically when designing a floating structure, it suggests that the designer should increase the width rather than deepen the depth of structure. It is because the effects of dissipating wave energy are more obvious when increasing the width than the depth.

Thesis (doctoral)--Friedrich-Wilhelms-Universität zu Berlin, 1879. / Vita.

Field Programmable Gate Arrays (FPGA) are increasingly being used to design high end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing standard, Leading One Predictor (LOP), and far and close data-path floating-point addition algorithms. Each algorithm has complex sub-operations which lead significantly to overall latency of the design. Each of the sub-operation is researched for different implementations and then synthesized onto a Xilinx Virtex2p FPGA device to be chosen for best performance. This thesis discusses in detail the best possible FPGA implementation for all the three algorithms and will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for Virtex2p architecture, one of the latest FPGA architectures provided by Xilinx. According to our results standard algorithm is the best implementation with respect to area but has overall large latency of 27.059 ns while occupying 541 slices. LOP algorithm improves latency by 6.5% on added expense of 38% area compared to standard algorithm. Far and close data-path implementation shows 19% improvement in latency on added expense of 88% in area compared to standard algorithm. The results clearly show that for area efficient design standard algorithm is the best choice but for designs where latency is the criteria of performance far and close data-path is the best alternative. The standard and LOP algorithms were pipelined into five stages and compared with the Xilinx Intellectual Property. The pipelined LOP gives 22% better clock speed on an added expense of 15% area when compared to Xilinx Intellectual Property and thus a better choice for higher throughput applications. Test benches were also developed to test these algorithms both in simulation and hardware. Our work is an important design resource for development of floating-point adder hardware on FPGAs. All sub components within the floating-point adder and known algorithms are researched and implemented to provide versatility and flexibility to designers as an alternative to intellectual property where they have no control over the design. The VHDL code is open source and can be used by designers with proper reference.

Field Programmable Gate Arrays (FPGA) are increasingly being used to design high end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing standard, Leading One Predictor (LOP), and far and close data-path floating-point addition algorithms. Each algorithm has complex sub-operations which lead significantly to overall latency of the design. Each of the sub-operation is researched for different implementations and then synthesized onto a Xilinx Virtex2p FPGA device to be chosen for best performance. This thesis discusses in detail the best possible FPGA implementation for all the three algorithms and will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for Virtex2p architecture, one of the latest FPGA architectures provided by Xilinx. According to our results standard algorithm is the best implementation with respect to area but has overall large latency of 27.059 ns while occupying 541 slices. LOP algorithm improves latency by 6.5% on added expense of 38% area compared to standard algorithm. Far and close data-path implementation shows 19% improvement in latency on added expense of 88% in area compared to standard algorithm. The results clearly show that for area efficient design standard algorithm is the best choice but for designs where latency is the criteria of performance far and close data-path is the best alternative. The standard and LOP algorithms were pipelined into five stages and compared with the Xilinx Intellectual Property. The pipelined LOP gives 22% better clock speed on an added expense of 15% area when compared to Xilinx Intellectual Property and thus a better choice for higher throughput applications. Test benches were also developed to test these algorithms both in simulation and hardware. Our work is an important design resource for development of floating-point adder hardware on FPGAs. All sub components within the floating-point adder and known algorithms are researched and implemented to provide versatility and flexibility to designers as an alternative to intellectual property where they have no control over the design. The VHDL code is open source and can be used by designers with proper reference.

No description available.

Floating point numbers are used in many applications that  would be well suited to a higher parallelism than that offered in a CPU. In  these cases, an FPGA, with its ability to handle multiple calculations  simultaneously, could be the solution. Unfortunately, floating point  operations which are implemented in an FPGA is often resource intensive,  which means that many developers avoid floating point solutions in FPGAs or  using FPGAs for floating point applications. Here the potential to get less expensive floating point operations by using ahigher radix for the floating point numbers and using and expand the existingDSP block in the FPGA is investigated. One of the goals is that the FPGAshould be usable for both the users that have floating point in their designsand those who do not. In order to motivate hard floating point blocks in theFPGA, these must not consume too much of the limited resources. This work shows that the floating point addition will become smaller withthe use of the higher radix, while the multiplication becomes smaller by usingthe hardware of the DSP block. When both operations are examined at the sametime, it turns out that it is possible to get a reduced area, compared toseparate floating point units, by utilizing both the DSP block and higherradix for the floating point numbers.

Digital Signal Processors (DSPs) have been an important component of all signal processing systems for over two decades now. Some of the obvious advantages of digital signal processing are the flexibility to make specific changes in the processing functions through hardware or software programming, faster processing speeds of the DSPs, cheaper storage, and retrieval of digital information and lower sensitivity to electrical noise. The explosive growth of wireless and signal processing applications has resulted in an increasing demand for such systems with low cost, low power consumption, and small form factors. With high--level of integration to single--chip systems, power consumption becomes a very important concern to be addressed. Intermediate--Frequency (IF) band signal processing requires the use of an array of DSPs, operating in parallel, to meet the speed requirements. This is a power intensive approach and makes use of certain communication schemes impractical in applications where power budget is limited. The front--end ADC and back--end DAC converters required in these systems become expensive when the signal is of wideband nature and a greater resolution is required. We present techniques to use floating--gate devices to implement signal processing systems in the analog domain in a power efficient and cost effective manner. Use of floating--gate devices mitigates key limitations in analog signal processing such as the lack of flexibility to specific changes in processing functions and the lack of programmability. This will impact the way a variety of signal processing systems are designed currently. It also enables array signal processing to be done in an area efficient manner. As will be shown through sample applications, this methodology promises to replace expensive wideband ADC and DAC converters with relatively easy to implement baseband data converters and an array of power intensive high speed DSPs with baseband DSPs. This approach is especially beneficial for portable systems where a lot of applications are running from a single battery.

The present work advances progress on the validation against measurements of linear and nonlinear rotordynamic models for predicting the dynamic shaft response of automotive turbochargers (TCs) supported on floating ring bearings. Waterfall spectra of measured shaft motions at the compressor and turbine ends of a test TC rotor evidences a complex response, showing synchronous (1X) and multiple subsynchronous frequencies along the entire operating speed range (maximum shaft speed ~ 65 krpm). Postprocessing of the raw test data by mathematical software allows filtering the synchronous and subsynchronous vibration components for later comparisons to predicted shaft motions. The static performance of the floating ring bearings is analyzed with in-house software (XLSFRBThermal®), which considers thermal expansion of the shaft and bearing components as well as static loading on the bearing due to lubricant feed pressure. In addition, the program calculates rotordynamic force coefficients for the inner and outer films of the floating ring bearing. The turbocharger Finite Element (FE) structural model for the linear and nonlinear analyses includes lumped masses for the compressor and turbine wheels and the thrust collar. The mass imbalance distribution on the TC rotor is estimated from the test data using a procedure derived from the two-plane balancing method with influence coefficients. The linear model yields predictions of rotor synchronous (1X) response to imbalance and damped eigenvalues. The analysis evidences that the rotor cylindrical-bending mode is unstable at all shaft speeds while the rotor conical model becomes more unstable as lubricant feed pressure decreases. The predicted synchronous (1X) motions agree well with the test data, showing a critical speed at approximately 20 krpm. The linear stability results indicate the existence of three critical speeds occurring at 4, 20 and 50 krpm. The second critical speed corresponds to the rotor cylindrical-bending mode, showing larger amplitudes of motion at the compressor nose than at the turbine end. The third critical speed associated to the rotor first bending modes is well damped. In the nonlinear transient analysis, the nonlinear equations of motion of the system (rotor-FRB) are integrated, and the bearing reaction forces are calculated at each time step in a numerical integration procedure. The model then yields predictions of total motion which is decomposed into synchronous (1X) and subsynchronous motions, amplitudes and frequencies. The nonlinear analysis predicts synchronous (1X) amplitudes that correlate well with the test data at high shaft speeds (> 30 krpm) but underpredicts the imbalance response at low shaft speeds (<30 krpm). The time transient simulations predict multiple frequency subsynchronous motions for shaft speeds ranging from 10 krpm to 55 krpm, with amplitudes and frequencies that are in good agreement with the measurements. Finally, the shaft motion measurements and predictions demonstrate that the turbocharger dynamic response does not depend greatly on the lubricant feed pressure and inlet temperature for the conditions tested.

In this thesis, according to the development of the vertical MOSFETs, we propose several MOSFETs that possess vertical channels, double gates, and buried oxide to solve the defects of the applications in switch devices, CMOS technique, and power devices. The vertical sidewall MOSFETs has many advantages, such as the packing density improvement, multiple channels, and independence on the critical lithography. Based on these characteristics, three kinds MOSFETs are now proposed. The first one is the vertical SOI MOSFET with smart source/ body contact (SSBVMOS). It is proposed to solve the floating body effect and self-heating effect. SSBVMOS provides a body-tie that does not occupy the excessive wafer area. It uses the smart source/body-tie to eliminate the unnecessary carriers and to provide an effective heat pass way. In addition, SSBVMOS is discussed with respect to the channel length and the buried oxide thickness adjustments, and also compared with the conventional vertical sidewall MOSFETs. The second one is the vertical MOSFET with upper and internal l-shape buried oxide (ULVMOS). ULVMOS uses the buried oxide to decrease the junction leakage. The ULVMOS also operates under the fully depleted regime to provide good characteristics. The last one is the novel embedded vertical sidewall MOSFETs (EGVMOS). EGVMOS maintains the advantages of the vertical structures and reduces the fabrication difficulty. It is also expected to decrease the overlap capacitance issue which affects the AC performance in the vertical sidewall MOSFET. As semiconductor channel length scaled down, the proposed devices is proved to provide effective applications for achieving good subthreshold swing, high on-off current ratio, and low DIBL through ISE-TCAD software simulation and real fabrication.