A time-independent finite-difference numerical scheme is developed to study the dynamic responses of both submerged , floating breakwater and composite floating breakwaters under wave force . The composite floating breakwaters is based on a moored floating bodies and submerged obstacle. The fully nonlinear kinematic free surface conditions and dynamic conditions are considered in the analysis .The numerical results were validated by several bench mark studies and existing reporting results. The wave reducing effect of both submerged, floating breakwaters and composite floating breakwaters were analysis and discussed¡C

In this thesis, according to the development of the vertical MOSFETs, we propose several MOSFETs that possess vertical channels, double gates, and buried oxide to solve the defects of the applications in switch devices, CMOS technique, and power devices. The vertical sidewall MOSFETs has many advantages, such as the packing density improvement, multiple channels, and independence on the critical lithography. Based on these characteristics, three kinds MOSFETs are now proposed. The first one is the vertical SOI MOSFET with smart source/ body contact (SSBVMOS). It is proposed to solve the floating body effect and self-heating effect. SSBVMOS provides a body-tie that does not occupy the excessive wafer area. It uses the smart source/body-tie to eliminate the unnecessary carriers and to provide an effective heat pass way. In addition, SSBVMOS is discussed with respect to the channel length and the buried oxide thickness adjustments, and also compared with the conventional vertical sidewall MOSFETs. The second one is the vertical MOSFET with upper and internal l-shape buried oxide (ULVMOS). ULVMOS uses the buried oxide to decrease the junction leakage. The ULVMOS also operates under the fully depleted regime to provide good characteristics. The last one is the novel embedded vertical sidewall MOSFETs (EGVMOS). EGVMOS maintains the advantages of the vertical structures and reduces the fabrication difficulty. It is also expected to decrease the overlap capacitance issue which affects the AC performance in the vertical sidewall MOSFET. As semiconductor channel length scaled down, the proposed devices is proved to provide effective applications for achieving good subthreshold swing, high on-off current ratio, and low DIBL through ISE-TCAD software simulation and real fabrication.

TCAD simulations have been performed using SILVACO ATLAS 2D device simulator for a Zero-Capacitor Random Access Memory, a new generation memory cell which is being researched as an alternative for DRAM memory cells in order to get rid of the bulky storage capacitor. In our study we have taken into consideration, a Dual Gate - ZRAM (DGZRAM) as it helps reduce drain-induced barrier lowering and hence leakage, while having better control of the charge in the substrate, The states are written into the device using impact ionization to generate a large number of holes in the substrate, which alter the threshold voltage of the device. The effect of the gate oxide thickness and substrate body thickness are being taken into consideration to increase the change in the threshold voltage and thereby the noise margin. A DGZRAM structure with a Quantum Well introduced into the substrate via a SiGe layer was also simulated. The quantum well introduces a hole storage pocket in the substrate. Comparisons in terms of noise margin, have been made for both the devices which show that the structure with the quantum well in the substrate performs better than the bulk structure. The effect of impact ionization on the electron and hole concentrations have been shown for both the devices. Simulations have been performed taking into consideration gate electrodes with different work functions and it has been observed that while n-polysilicon has a detrimental impact in MOSFETs due to high off-state leakage current, it can be used to obtain low power memory cells. Parameters such as the quantum well doping, composition of Ge in the quantum well, channel length of the device, SiGe layer thickness and its position with respect to the top gate have been varied to obtain the optimum noise margin for the device.

Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic. We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

In this paper, we propose a novel thin film MOSFET with source/drain tie and discontinuously block oxide layers. Improving process is very important, when the gate length of SOI MOSFET is reduced. To overcome the misalignment problem, we use self-aligned technology to fabricate this device. In addition, the device has discontinuously block oxide layers; they can improve short channel effects, reduce the parasitic capacitance, and decrease the leakage current cause by P-N junction between source/drain and body regions. They also supply two pass ways to eliminate carriers and heat which generated by impact ionization resulting in suppression of floating-body effect and self-heating effect. In addition, these two pass ways can be seen as the parallel equivalent resistance results in a reduced series resistance and an increased drain saturation current. According to the ISE TCAD 10.0 simulation results, the discontinuously block oxide layers can not only improve the short channel effects, but also eliminate the floating-body effect and diminish the self-heating effect because of the pass ways.

In this thesis, we present a new Poly - Si TFT process method to overcome Self - heating effect and Floating body effect. The main drawback of a conventional Poly - Si TFT is the existence of self - heating effect and floating body effect. The self - heating effect leads to drain current reduced and the floating body effect leads to premature device breakdown and kink effects. Here, we utilize all kinds of different isolation technologies to form non - continuing buried layer. Between the non - continuing buried layer there are pass ways, which contact the active region and the substrate directly. Because of conventional LOCOS isolation technology has longer bird¡¦s beak, the familiar method of SILO and PBL isolation technologies are used to reduce bird¡¦s beak. Also, we use STI isolation technology to build up non - continuing buried layer, which can control the width of pass way more easily. It is proved from the measurement that the pass way can slow down the self - heating effect and the floating body effect successfully.

Esta dissertação apresenta os resultados obtidos no estudo do funcionamento dinâmico de uma célula de memória composta por um único transistor SOI MOSFET. Este estudo é baseado nos resultados experimentais observados em dispositivos nMOSFET em tecnologia SOI desenvolvidos no imec, Leuven, Bélgica. Os dados experimentais apresentados foram obtidos no Laboratório de Sistemas Integráveis (LSI) da Escola Politécnica da Universidade de São Paulo (EPUSP) e nos laboratórios AMSIMEC do centro de pesquisa imec, Bélgica. No presente trabalho foi levantado o histórico das memórias dinâmicas, assim como as características fundamentais de uma célula de memória dinâmica de um único transistor, tais como tempo de retenção e margem de sensibilidade, que são definidas e posteriormente verificadas para diferentes tipos de transistores. Inicialmente, foram estudados os mecanismos capazes de promover algum tipo de histerese na curva de corrente de fonte-dreno em função da tensão de porta de um transistor SOI em DC. Por meio destas propriedades, muitas vezes vistas como parasitárias, foi possível explorar o comportamento de um único transistor como célula de memória. Em seguida, passou-se às medidas dinâmicas, momento no qual foi necessário desenvolver um arranjo experimental conveniente de forma que fosse possível medir pulsos da ordem de µA com duração da ordem de 10ns. Assim, uma parte desta dissertação é dedicada à descrição dos problemas e soluções encontrados para viabilizar a medida destes rápidos e pequenos sinais. Foram observados dispositivos com tempos de retenção superiores a 100ms e margens de sensibilidades que ultrapassam 100µA. Finalmente, são apresentadas as conclusões encontradas e as possibilidades para estudos futuros. / This masters thesis presents the results obtained throughout the study of a memory cell composed of a single SOI MOSFET transistor. This study is based on the experimental results observed on SOI nMOSFET devices developed at imec, Leuven, Belgium. The experimental data presented was obtained both at the Laboratório de Sistemas Integráveis (LSI) from the Escola Politécnica da USP (EPUSP) and the AMSIMEC laboratories in the imec research center, Belgium. In this work, the history of dynamic memories as well as the fundamental characteristics of a single transistor dynamic memory cell, such as retention time and sense margin, which are defined and later verified for different transistors, have been analysed. Initially, the mechanisms capable of leading to some sort of hysteresis on the drain-source current as a function of the gate voltage on a SOI transistor operating in DC were studied. Through these properties many times regarded as parasitic it was possible to explore the behavior of a single SOI transistor operating as a memory cell. Afterwards, this work analyzes dynamic measurements, for which it has been necessary to develop an appropriate experimental setup capable of measuring pulses of some µA and lasting approximately 10ns. Therefore, part of this thesis is reserved for the description of the problems and solutions found in order to enable the measurement of these fast and small signals. Devices with retention times larger than 100ms and sense margins surpassing 100µA were measured. Finally, conclusions and possible future studies are presented.

Esta dissertação apresenta os resultados obtidos no estudo do funcionamento dinâmico de uma célula de memória composta por um único transistor SOI MOSFET. Este estudo é baseado nos resultados experimentais observados em dispositivos nMOSFET em tecnologia SOI desenvolvidos no imec, Leuven, Bélgica. Os dados experimentais apresentados foram obtidos no Laboratório de Sistemas Integráveis (LSI) da Escola Politécnica da Universidade de São Paulo (EPUSP) e nos laboratórios AMSIMEC do centro de pesquisa imec, Bélgica. No presente trabalho foi levantado o histórico das memórias dinâmicas, assim como as características fundamentais de uma célula de memória dinâmica de um único transistor, tais como tempo de retenção e margem de sensibilidade, que são definidas e posteriormente verificadas para diferentes tipos de transistores. Inicialmente, foram estudados os mecanismos capazes de promover algum tipo de histerese na curva de corrente de fonte-dreno em função da tensão de porta de um transistor SOI em DC. Por meio destas propriedades, muitas vezes vistas como parasitárias, foi possível explorar o comportamento de um único transistor como célula de memória. Em seguida, passou-se às medidas dinâmicas, momento no qual foi necessário desenvolver um arranjo experimental conveniente de forma que fosse possível medir pulsos da ordem de µA com duração da ordem de 10ns. Assim, uma parte desta dissertação é dedicada à descrição dos problemas e soluções encontrados para viabilizar a medida destes rápidos e pequenos sinais. Foram observados dispositivos com tempos de retenção superiores a 100ms e margens de sensibilidades que ultrapassam 100µA. Finalmente, são apresentadas as conclusões encontradas e as possibilidades para estudos futuros. / This masters thesis presents the results obtained throughout the study of a memory cell composed of a single SOI MOSFET transistor. This study is based on the experimental results observed on SOI nMOSFET devices developed at imec, Leuven, Belgium. The experimental data presented was obtained both at the Laboratório de Sistemas Integráveis (LSI) from the Escola Politécnica da USP (EPUSP) and the AMSIMEC laboratories in the imec research center, Belgium. In this work, the history of dynamic memories as well as the fundamental characteristics of a single transistor dynamic memory cell, such as retention time and sense margin, which are defined and later verified for different transistors, have been analysed. Initially, the mechanisms capable of leading to some sort of hysteresis on the drain-source current as a function of the gate voltage on a SOI transistor operating in DC were studied. Through these properties many times regarded as parasitic it was possible to explore the behavior of a single SOI transistor operating as a memory cell. Afterwards, this work analyzes dynamic measurements, for which it has been necessary to develop an appropriate experimental setup capable of measuring pulses of some µA and lasting approximately 10ns. Therefore, part of this thesis is reserved for the description of the problems and solutions found in order to enable the measurement of these fast and small signals. Devices with retention times larger than 100ms and sense margins surpassing 100µA were measured. Finally, conclusions and possible future studies are presented.

A 2D fully nonlinear Numerical Wave Tank (NWT) is developed based on the potential theory, mixed Eulerian-Lagrangian (MEL) time marching scheme, and boundary element method (BEM). Nonlinear Wave deformation and wave forces on stationary and freely floating bodies are calculated using the NWT. For verification, the computed mean, 1st, 2nd, and 3rd order wave forces on a single submerged cylinder are compared with those of Chaplin's experiment, Ogilvie's 2nd-order theory, and other nonlinear computation called high-order spectral method. Similar calculations for dual submerged cylinders are also conducted. The developed fully nonlinear NWT is also applied to the calculations of the nonlinear pressure and force of surface piercing barge type structures and these obtained results agree with experimental and theoretical results. Nonlinear waves generated by prescribed body motions, such as wedge type wave maker or land sliding in the coastal slope area, can also be simulated by the developed NWT. The generated waves are in agreement with published experimental and numerical results. Added mass and damping coefficients can also be calculated from the simulation in time domain. For the simulation of freely floating barge-type structure, only fully nonlinear time-stepping scheme can accurately produce nonlinear body motions with large floating body simulations. The acceleration potential method, which was developed by Tanizawa (1996), is known to be the most accurate, consistent and stable. Using acceleration potential method, in the present study, the series of motions and drift forces were calculated over a wide range of incident wave frequencies including resonance region. To guarantitatively compare the nonlinear contribution of free-surface and body-boundary conditions, the body-nonlinear-only case with linearized free-surface condition is separately simulated. All the floating body motions and forces are in agreement with experimental results. Finally, the NWT is extended to fully nonlinear wave-body-current interactions of freely floating bodies, which has not been published in the open literature until now.

In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.