This article focuses on ¡§Floating Body Effect¡¨ of PD-SOI (partial depletion silicon-on-insulator), because the conventional PD-SOI 1T DRAM (one transistor of dynamic random access memory) cell can¡¦t be held impact ionization produced carriers efficiently, so it is unable to provide reliable programming window. In this article, we propose a new device with its special structure, besides adding ¡§Block Oxide¡¨ to the two sides of device body to strengthen ¡§kink effect¡¨, we also add a negative bias to the beneath electrode which is located in the bottom of U-cave of this device, this design can manipulate ¡§kink effect¡¨ more feasibly, and guarantee the hole-held ability. Those points can improve performance of PD-SOI 1T DRAM cell greatly. The new SOI device contains four advantages in the below: 1. Exploiting conventional bulk Si-wafer for manufacture, no expensive SOI wafer needs. 2. Increasing programming window of 1T DRAM cell greatly. 3. Preventing ¡§Pinch off¡¨ occurs in source and drain depletion region. 4. Reducing the junction capacitor of Source-Body and Drain-Body. We use simulation tool, ISE TCAD 10.0 to simulate structure of this new device, and do I-V characteristic electric analyze to this device. In the manufacture, thanks for the equipment and facility of NDL (National Device Laboratory); we apply to this resource to realize our devices.

Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic. We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

In this thesis, we propose a new thin-film transistor with trenched body and airgap-insulated structure (AITFT) for one-transistor dynamic random access memory (1T-DRAM) applications and investigate the influence of different materials on the sensing current window and retention time. Its basic operation mechanisms are based on the impact ionization and floating body effects. Due to the generated holes storing in the pseudo neutral region, the threshold voltage (Vth) is lower, resulting in a high drain current for state ¡§1¡¨. So we can recognize the data by sensing the difference of the drain current. According to the ISE TCAD 10.0 simulations, owing to the design of trench and airgap-isolation structure, the AITFT can enhance about 212% sensing current window and 42% retention time compared with the conventional TFT at the channel length of 150 nm and temperature of 300K conditions. Also, owing to the source/drain-tie, the generated heat can be dissipated quickly from the source/drain to the substrate thus the thermal instability is improved. In other words, the AITFT can improve the thermal reliability but without losing control of the short-channel effects.

Durant les 5 dernières décennies, les technologies CMOS se sont imposées comme méthode de fabrication principale pour les circuits semi-conducteurs intégrés avec notamment le transistor MOSFET. Néanmoins, la miniaturisation de ces transistors en technologie CMOS sur substrat massif atteint ses limites et a donc été arrêtée. Les filières FDSOI apparaissent comme une excellente alternative permettant une faible consommation et une excellente maîtrise des effets électrostatiques dans les transistors MOS, même pour les nœuds technologiques 14 et 28 nm. Cependant, la pente sous le seuil (60 mV/décade) du MOSFET ne peut pas être améliorée, ce qui limite la réduction de la tension d’alimentation. Cette restriction a motivé la recherche de composants innovants pouvant offrir des déclenchements abrupts tels que le Z2-FET (Zéro pente sous le seuil et Zéro ionisation par impact), Z2-FET DGP (avec double Ground Plane) et Z3-FET (Zéro grille avant). Grace à leurs caractéristiques intéressantes (déclenchement abrupte, faible courant de fuite, tension de déclenchement ajustable, rapport de courant ION/IOFF élevé), les dispositifs à modulation de bandes peuvent être utilisés dans différentes applications. Dans ce travail, nous nous sommes concentrés sur la protection contre les décharges électrostatiques (ESD), la mémoire DRAM embarquée sans capacité de stockage, et les interrupteurs logiques. L’étude des mécanismes statique et transitoire ainsi que des performances de ces composants a été réalisée grâce à des simulations TCAD détaillées, validées systématiquement par des résultats expérimentaux. Un modèle de potentiel de surface pour les trois dispositifs est également fourni. / During the past 5 decades, Complementary Metal Oxide Semiconductor (CMOS) technology was the dominant fabrication method for semiconductor integrated circuits where Metal Oxide Semiconductor Field Effect Transistor (MOSFET) was and still is the central component. Nonetheless, the continued physical downscaling of these transistors in CMOS bulk technology is suffering limitations and has been stopped nowadays. Fully Depleted Silicon-On-Insulator (FDSOI) technology appears as an excellent alternative that offers low-power consumption and improved electrostatic control for MOS transistors even in very advanced nodes (14 nm and 28 nm). However, the 60 mV/decade subthreshold slope of MOSFET is still unbreakable which limits the supply voltage reduction. This motivated us to explore alternative devices with sharp-switching: Z2-FET (Zero subthreshold slope and Zero impact ionization), Z2-FET DGP (with Dual Ground Planes) and Z3-FET (Zero front-gate). Thanks to their attractive characteristics (sharp switch, low leakage current, adjustable triggering voltage and high current ratio ION/IOFF), band-modulation devices are envisioned for multiple applications. In this work, we focused on Electro-Static Discharge (ESD) protection, capacitor-less Dynamic Random Access Memory and fast logic switch. The DC and transient operation mechanisms as well as the device performance are investigated in details with TCAD simulations and validated with systematic experimental results. A compact model of surface potential distribution for all Z-FET family devices is also given.

In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.