This paper investigates the device behavior of a novel pseudo tri-gate ultrathin channel vertical MOSFET with source/drain tie (S/D tie), the PTG-SDT VMOS. The S/D tie (SDT) of this novel device circumvents short channel effect (SCEs). A double- surround-gate (the mid-gate and the spacer gate) is also presented to investigate the effect of S/D tie. According to the 2D simulation, three kinds of pseudo vertical MOSFETs are now proposed. The first one is to investigate the device characteristics of the new PTG-SDT VMOS. Our proposed structure also mitigates self-heating effect (SHEs), thereby enhancing the drain drive current and the thermal stability. Owing to its ultrathin channel (Tsi = 10 nm), the PTG-SDT VMOS has a very low subthreshold swing of 60 mV/dec, for channel lengths from 90 nm down to 40 nm. It is also found to control drain-induced barrier lowing (DIBL) and to have an excellent Gm of 4.5 mS/£gm at the channel length 40 nm. The second one, we proposed the ultrathin channel pseudo tri-gate vertical MOSFET with natural source/drain tie (NSDT), the big source/drain tie (BSDT), the SDT and the without source/drain tie (WSDT) VMOS. The PTG VMOS of this novel structure circumvents short channel effects (SCEs). A new natural S/D tie (N-SDT) is also presented to investigate of the PTG VMOS. According to 2D simulation, the PTG-NSDT also show the excellent thermal dissipated such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 47% and 66% respectively, thereby enhancing the ON-state and OFF-state current ratio. In addition, the dependence of GIDL current on body bias and temperature is characterized and discussed when the source and drain interchanged. Although the PTG VMOS keep the double-surround-gate and S/D tie structure, the design flow is more simplify even increase the drain drive current and immunity the SHEs.

In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.

We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al₂O₃ dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices. Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.