Floating offshore wind turbines have the potential to become a significant source of affordable renewable energy. However, their strong interactions with both wind- and wave-induced forces raise a number of technical challenges in both modelling and design. This thesis takes aim at some of those challenges. One of the most uncertain modelling areas is the mooring line dynamics, for which quasi-static models that neglect hydrodynamic forces and mooring line inertia are commonly used. The consequences of using these quasi-static mooring line models as opposed to physically-realistic dynamic mooring line models was studied through a suite of comparison tests performed on three floating turbine designs using test cases incorporating both steady and stochastic wind and wave conditions. To perform this comparison, a dynamic finite-element mooring line model was coupled to the floating wind turbine simulator FAST. The results of the comparison study indicate the need for higher-fidelity dynamic mooring models for all but the most stable support structure configurations. %It was also observed that small inaccuracies in the platform motion time series introduced by a quasi-static mooring model can cause much larger inaccuracies in the time series of the rotor blade dynamics. Industry consensus on an optimal floating wind turbine configuration is inhibited by the complex support structure design problem; it is difficult to parameterize the full range of design options and intuitive tools for navigating the design space are lacking. The notion of an alternative, ``hydrodynamics-based'' optimization approach, which would abstract details of the platform geometry and deal instead with hydrodynamic performance coefficients, was proposed as a way to obtain a more extensive and intuitive exploration of the design space. A basis function approach, which represents the design space by linearly combining the hydrodynamic performance coefficients of a diverse set of basis platform geometries, was developed as the most straightforward means to that end. Candidate designs were evaluated in the frequency domain using linearized coefficients for the wind turbine, platform, and mooring system dynamics, with the platform hydrodynamic coefficients calculated according to linear hydrodynamic theory. Results obtained for two mooring systems demonstrate that the approach captures the basic nature of the design space, but further investigation revealed limitations on the physical interpretability of linearly-combined basis platform coefficients.. A different approach was then taken for exploring the design space: a genetic algorithm-based optimization framework. Using a nine-variable support structure parameterization, this framework is able to span a greater extent of the design space than previous approaches in the literature. With a frequency-domain dynamics model that includes linearized viscous drag forces on the structure and linearized mooring forces, it provides a good treatment of the important physical considerations while still being computationally efficient. The genetic algorithm optimization approach provides a unique ability to visualize the design space. Application of the framework to a hypothetical scenario demonstrates the framework's effectiveness and identifies multiple local optima in the design space -- some of conventional configurations and others more unusual. By optimizing to minimize both support structure cost and root-mean-square nacelle acceleration, and plotting the design exploration in terms of these quantities, a Pareto front can be seen. Clear trends are visible in the designs as one moves along the front: designs with three outer cylinders are best below a cost of \$6M, designs with six outer cylinders are best above a cost of \$6M, and heave plate size increases with support structure cost. The complexity and unconventional configuration of the Pareto optimal designs may indicate a need for improvement in the framework's cost model. / Graduate / 0548 / mtjhall@uvic.ca

While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datapath merging to minimize area. The methodology reduces the subset of floating-point instructions implemented to the minimum required for the application. Datapath merging is then performed on the required datapaths to minimize area. Previous datapath merging techniques failed to consider merging components of different bit-widths and thus ignore the bit-alignment problem in datapath merging. This thesis presents a novel bit-alignment solution during datapath merging. In creating the custom FPU, the subset of floating-point instructions that should be implemented in hardware has to be determined. Implementing more instructions in hardware reduces the cycle count of the application, but may lead to increased delay due to multiplexers inserted on the critical path during datapath merging. A rapid design space exploration was performed to explore the trade-offs. By performing this exploration, a designer could determine the number of instructions that should be implemented as a custom FPU and the number that should be left for software emulation, such that performance and area meets the designer's requirements. Customized FPUs were generated for different Mediabench applications and compared to a fully-featured reference FPU that implemented all floating-point operations. Reducing the floating-point instruction set reduced the FPU area by an average of 55%. Performing instruction reduction and then datapath merging reduced the FPU area by an average of 68%. Experiments showed that datapath merging without bit-alignment achieved an average area reduction of 10.1%. With bit-alignment, an average of 16.5% was achieved. Bit-alignment proved most beneficial when there was a diverse mix of different bit-widths in the datapaths. Performance of Field-Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, they waste area on the FPGA die. To overcome this issue, a novel flexible multi-mode embedded FPU for FPGAs is presented in this thesis that can be configured to perform a wide range of operations. The floating-point adder and multiplier in the embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. It is also capable of floating-point and integer multiply-add operations. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on the FPGA with embedded FPU blocks. The implementations on the FPGA with embedded FPUs showed mean area and delay improvements of 5.2x and 5.8x respectively for the double-precision benchmarks, and 4.4x and 4.2x for the single-precision benchmarks.

While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datapath merging to minimize area. The methodology reduces the subset of floating-point instructions implemented to the minimum required for the application. Datapath merging is then performed on the required datapaths to minimize area. Previous datapath merging techniques failed to consider merging components of different bit-widths and thus ignore the bit-alignment problem in datapath merging. This thesis presents a novel bit-alignment solution during datapath merging. In creating the custom FPU, the subset of floating-point instructions that should be implemented in hardware has to be determined. Implementing more instructions in hardware reduces the cycle count of the application, but may lead to increased delay due to multiplexers inserted on the critical path during datapath merging. A rapid design space exploration was performed to explore the trade-offs. By performing this exploration, a designer could determine the number of instructions that should be implemented as a custom FPU and the number that should be left for software emulation, such that performance and area meets the designer's requirements. Customized FPUs were generated for different Mediabench applications and compared to a fully-featured reference FPU that implemented all floating-point operations. Reducing the floating-point instruction set reduced the FPU area by an average of 55%. Performing instruction reduction and then datapath merging reduced the FPU area by an average of 68%. Experiments showed that datapath merging without bit-alignment achieved an average area reduction of 10.1%. With bit-alignment, an average of 16.5% was achieved. Bit-alignment proved most beneficial when there was a diverse mix of different bit-widths in the datapaths. Performance of Field-Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, they waste area on the FPGA die. To overcome this issue, a novel flexible multi-mode embedded FPU for FPGAs is presented in this thesis that can be configured to perform a wide range of operations. The floating-point adder and multiplier in the embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. It is also capable of floating-point and integer multiply-add operations. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on the FPGA with embedded FPU blocks. The implementations on the FPGA with embedded FPUs showed mean area and delay improvements of 5.2x and 5.8x respectively for the double-precision benchmarks, and 4.4x and 4.2x for the single-precision benchmarks.

Thesis (Ph. D.)--University of Texas at Austin, 2009. / Title from PDF title page (University of Texas Digital Repository, viewed on Sept. 9, 2009). Vita. Includes bibliographical references.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2005. / Includes bibliographical references (p. 81-86).

A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.

Free-floating planets (FFPs) are very difficult to observe directly since they are isolated and intrinsically faint. The gravitational microlensing effect is now major method to observe FFPs, but observing low-mass FFPs is still difficult due to their short duration. We compute simulations for FFP microlensing observations down to Earth-mass using the numerical Besancon Galactic model created by Robin et al. (2012a). These are the first detailed simulation of FFP microlensing using a population synthesis Galactic model incorporating a 3D extinction model, and we also take full account of finite source effects. Firstly, we simulate the microlensing event rate and spatial distribution using three different modes, and for each mode three FFP lens masses (Jupiter, Neptune, and Earth). For the target area of (l, b) =(1, -1.75) which corresponds to the centre of the proposed Euclid ExELS field, our simulations result in 184-920 Jupiter-mass FFPs during the 5 year Euclid mission depending on simulation assumptions. For the Earth-mass FFPs, the rate range is 9-49 FFPs assuming 100% detection efficiency. Next, we compute the rate of parallax detection using a 3D model of the observers. We consider parallax detection by Euclid and WFIRST-AFTA, and by Euclid and LSST. We found that 52 Jupiter-mass FFPs will be detected by a parallax between Euclid and WFIRST-AFTA for two 30-day continuous period around equinoxes if they observe simultaneously. The rate falls to 4 parallax events for Earth-mass FFPs. The parallax detection between Euclid and LSST would be affected by the observation time on the Earth, but it could provide 20 Jupiter-mass FFPs down to 1.4 Earth-mass FFPs.

QC 20110620

The ionosphere is a conducting layer in the Earth's upper atmosphere and is the nearest naturally occurring plasma environment. Inherent to all plasma environments is an electric field. Currently, the double electric field probe is the most successful instrument for measuring the electric fields of space plasmas. Utah State University/Space Dynamics Lab has developed a double electric field probe, called the Floating Potential Probe (FPP), with a slightly different instrumentation approach than what has been done previously. The FPP is one component of a suite of instruments that launched in fall of 2007 from Wallops Island, Virginia, as part of NASA's sounding rocket program to an approximate altitude of 450km. This mission is nicknamed "The Storms Mission.'' In general, an electric field probe acts as a voltmeter to measure the electric potential between a probe located near the end of a long boom and the skin of the rocket. This measurement is also called the floating potential. To obtain electric field measurements, the floating potential is gathered from two probes located 180 degrees apart and differenced to calculate the electric potential between probes and thereby the ambient electric field. Historically, this has been accomplished with an entirely analog circuit implementation. For the Storm Mission, the signals are digitized before the differencing occurs. Then during data analysis, the signals can either be differenced digitally to produce the ambient electric field or summed to observe the floating potential of the payload skin. Additionally, the signals are digitized to 20 bits giving a far greater dynamic range than is typically achieved in similar direct current (DC) coupled instruments. This thesis discusses the theory, design, test, and calibration efforts of the FPP for the Storms Mission.

Rivers are integral parts of Bangladesh & Bengali people’s life. The whole country is criss-crossed by more than 700 rivers including their tributaries. In other words, rivers formed this country as a delta and have been contributing to spring life to this land with agriculture, food, electricity, transportation, and tranquil beauty, creating opportunity for different occupations, and providing very comfortable moderate climate. Due to over population and urban sprawl, the current development pattern of the country is culminating in filling up wetlands, changing the course of lakes, narrowing down and in some cases killing rivers for urban development leaving great impact on environment. As a consequence, the country is being affected by frequent flood, deforestation, surge, cyclones, and rise of sea level due to global warming. The concern for introducing an adoptive sustainable architecture that interacts with rivers and water, protects environment as well as facilitates new developments has been noticed by scientists and scholars from every sector of development. This thesis will be emphasizing on establishing some unique architectural features that would especially be applicable for riverfront architectures, that leaves least impact on nature and respects the country’s tradition, heritage and lifestyle which are inseparable from rivers.