This thesis presents a generalized approach for the fully digital design and implementation of chaos generators through the numerical solution of chaotic ordinary differential equations. In particular, implementations use the Euler approximation with a fixed-point twos complement number representation system for optimal hardware and performance. In general, digital design enables significant benefits in terms of power, area, throughput, reliability, repeatability and portability over analog implementations of chaos due to lower process, voltage and temperature sensitivities and easy compatibility with other digital systems such as microprocessors, digital signal processing units, communication systems and encryption systems. Furthermore, this thesis introduces the idea of implementing multidimensional chaotic systems rather than 1-D chaotic maps to enable wider throughputs and multiplier-free architectures that provide significant performance and area benefits. This work focuses efforts on the well-understood family of autonomous 3rd order "jerk" chaotic systems. The effect of implementation precision, internal delay cycles and external delay cycles on the chaotic response are assessed. Multiplexing of parameters is implemented to enable switching between chaotic and periodic modes of operation. Enhanced chaos generators that exploit long-term divergence in two identical systems of different precision are also explored. Digital design is shown to enable real-time controllability of 1D multiscroll systems and 4th order hyperchaotic systems, essentially creating non-autonomous chaos that has thus far been difficult to implement in the analog domain. Seven different systems are mathematically assessed for chaotic properties, implemented at the register transfer level in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA. The statistical properties of the output are rigorously studied using the NIST SP. 800-22 statistical testing suite. The output is adapted for pseudo random number generation by truncating statistically defective bits. Finally, a novel post-processing technique using the Fibonacci series is proposed and implemented with a non-autonomous driven hyperchaotic system to provide pseudo random number generators with high nonlinear complexity and controllable period length that enables full utilization of all branches of the chaotic output as statistically secure pseudo random output.

This paper presents the design of a reconfigurable asynchronous unit, called the pulsed quad-cell (PQ-cell), for conformal computing. The conformal computing vision is to create computational materials that can conform to the physical and computational needs of an application. PQ-cells, like cellular automata, are assembled into arrays with nearest neighbor communication and are capable of general computation. They operate asynchronously to minimize power consumption and to allow sealing without the limitations imposed by a global clock. Cell operations are stimulated by pulses which use two wires to encode a data bit. Cells are individually reconfirgurable to perform logic, move and store information, and coordinate parallel activity. The PQ-cell design targets a 0.25 μm CMOS technology. Simulation results show that a PQ-cell, when pulsed at 1.3 GHz, consumes 16.9 pJ per operation. Examples of self-timed multi-cell structures include a 98 MHz ring oscillator and a 385 MHz pipeline.

abstract: With the exponential growth in video content over the period of the last few years, analysis of videos is becoming more crucial for many applications such as self-driving cars, healthcare, and traffic management. Most of these video analysis application uses deep learning algorithms such as convolution neural networks (CNN) because of their high accuracy in object detection. Thus enhancing the performance of CNN models become crucial for video analysis. CNN models are computationally-expensive operations and often require high-end graphics processing units (GPUs) for acceleration. However, for real-time applications in an energy-thermal constrained environment such as traffic management, GPUs are less preferred because of their high power consumption, limited energy efficiency. They are challenging to fit in a small place. To enable real-time video analytics in emerging large scale Internet of things (IoT) applications, the computation must happen at the network edge (near the cameras) in a distributed fashion. Thus, edge computing must be adopted. Recent studies have shown that field-programmable gate arrays (FPGAs) are highly suitable for edge computing due to their architecture adaptiveness, high computational throughput for streaming processing, and high energy efficiency. This thesis presents a generic OpenCL-defined CNN accelerator architecture optimized for FPGA-based real-time video analytics on edge. The proposed CNN OpenCL kernel adopts a highly pipelined and parallelized 1-D systolic array architecture, which explores both spatial and temporal parallelism for energy efficiency CNN acceleration on FPGAs. The large fan-in and fan-out of computational units to the memory interface are identified as the limiting factor in existing designs that causes scalability issues, and solutions are proposed to resolve the issue with compiler automation. The proposed CNN kernel is highly scalable and parameterized by three architecture parameters, namely pe_num, reuse_fac, and vec_fac, which can be adapted to achieve 100% utilization of the coarse-grained computation resources (e.g., DSP blocks) for a given FPGA. The proposed CNN kernel is generic and can be used to accelerate a wide range of CNN models without recompiling the FPGA kernel hardware. The performance of Alexnet, Resnet-50, Retinanet, and Light-weight Retinanet has been measured by the proposed CNN kernel on Intel Arria 10 GX1150 FPGA. The measurement result shows that the proposed CNN kernel, when mapped with 100% utilization of computation resources, can achieve a latency of 11ms, 84ms, 1614.9ms, and 990.34ms for Alexnet, Resnet-50, Retinanet, and Light-weight Retinanet respectively when the input feature maps and weights are represented using 32-bit floating-point data type. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2019

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This research provides the real-time computational resource for three dimensional tomographic chemical threat mapping using mobile hyperspectral sensors from sparse input data. The crucial calculation limiting real-time execution of the algorithm is the determination of the projection matrix using the algebraic reconstruction technique (ART). The computation utilizes the inherent parallel nature of ART with an implementation of the algorithm on a field programmable gate array. The MATLAB Fixed-Point Toolbox is used to determine the optimal fixed-point data types in the conversion from the original floating-point algorithm. The computation is then implemented using the Xilinx System Generator, which generates a hardware description language representation from a block diagram design. / Electrical and Computer Engineering

Recently, the advent of the integrated circuits (ICs), the monolithic microwave integrated circuits (MMICs) and the multiprocessing computer technology have provided numerous opportunities to make the radar technology compact and affordable. The ultra-wideband (UWB) technology gives many advantages over the traditional narrowband radar systems due to its high spatial resolution, low susceptibility to interference, superior penetration depths, and increased peak power. However, the ability to digitize and reconstruct the full UWB signal spectrum comes at a considerable cost and size. Ultimately, high-speed sampling rates above 10 giga-samples per second (GSPS) are beyond the abilities of conventional analog-to-digital converters (ADCs). The UWB technology is inaccessible to the end-user for various advanced applications in microwave imaging and detection. The purpose of this work is to provide a low-cost, dual-channel UWB pulsed-radar system that is readily available with a 1:10 system bandwidth. The advancements in low-cost alternatives for compact and portable designs empower many promising UWB applications. Here, the desired bandwidth is from 500 MHz to 5 GHz, which utilizes a fast pulse repetition frequency (PRF) in short-range applications. The preliminary results from the novel Equivalent-Time Sampling Receiver are promising with an equivalent-time sampling rate up to 20 GSPS. Nevertheless, the system design is versatile for bandwidth tuning in order to meet the needs of different applications. This versatility is enabled by: i) selection of the effective sampling rate through the field-programmable gate array (FPGA) programming environment, ii) choice of the receivers' front-end track and hold (T & H) amplifier bandwidth, iii) a collection of different PRFs from the low kilohertz up to 20 MHz, iv) tuning of the pulse generator bandwidth, and v) simultaneous multi-channel capabilities enabling antenna beam-forming, polarization diversity and spatial diversity. The result is a fully functional prototype that costs a fraction of traditional bench-top solutions. / Thesis / Master of Applied Science (MASc)