[pt] O objetivo desta dissertação consiste no desenvolvimento de um analisador de erro para Redes Ópticas através da utilização de circuitos integrados programáveis operando na taxa do Gigabit. As principais fontes de erro, as técnicas de medição da taxa de bits errados e a avaliação de desempenho de enlaces elétricos e ópticos em redes de telecomunicações são descritas e caracterizadas. Dispositivos de transmissão e recepção são desenvolvidos através da introdução de ferramentas computacionais para FPGA colocando-se em evidência o mecanismo de alinhamento e sincronização entre os dois. As simulações e análises destes dispositivos são apresentadas possibilitando a inserção destes em um módulo capaz de avaliar o desempenho de um enlace óptico na taxa de 1.25Gbit/s em função da taxa de bits errados. / [en] The objective of this dissertation consist on development of an error analyzer for Optical Networks by the use of programmable integrated circuits operating in Gigabit rates. The main sources of error, the techniques of BER measurement and the performance evaluation of the electric and optical links in telecommunication networks are described and characterized. Transmission and reception devices are developed through the introduction of computational tools for FPGA giving emphasis to alignment and synchronization mechanism between the two. The simulations and analyses of these devices are presented making possible the insertion of these in a module capable to evaluate the performance of the optical link in the 1.25Gbit/s rate in function of the BER.

Neste trabalho, é apresentado o desenvolvimento de um IP de rede Ethernet com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. O IPC foi adaptado do projeto Ethernet_tri_mode, e é capaz de transferir dados a velocidades de 1000, 100 e 10 Mbps. O desenvolvimento envolveu a adaptação do código para atingir os requisitos do projeto, feito segundo as diretrizes do CIERMag de manter todo o código em VHDL. Além disso, foi implementada uma interface de comunicação com o processador Nios II para tornar possível a configuração do sistema, bem como a transferência de dados através de um software sendo executado no processador. O IPC Ethernet foi projetado para ser aplicado no espectrômetro digital em desenvolvimento pelo CIERMag e teve como compromissos a baixa utilização de recursos lógicos do FPGA e, ao mesmo tempo, a disponibilização de uma alta taxa de transferência de dados para o espectrômetro. Como ferramenta de desenvolvimento, foi utilizada a plataforma Quartus II cujo fornecedor é a Altera. Já os testes em placa foram realizados em um kit de desenvolvimento DE3-150 da Terasic, o qual utiliza uma FPGA Stratix III, também da Altera. Com o intuito de testar e validar o sistema, foi desenvolvido um software para o processador Nios II capaz de receber e enviar dados através do IPC e com inteligência para responder pedidos do tipo ARP e PING. O subsistema de Gigabit Ethernet desenvolvido aqui já incorpora a versão corrente do Espectrômetro Digital de RM do CIERMag. / In this work we expose the implementation of an Ethernet network core which interfaces to Avalon bus used along with the Nios II Altera processor. This core was adapted from the Ethernet_tri_mode project. It can transfer data at rates of 1000, 100 and 10 Mbps. The development involved the adaptation of the code to fullfil the project requirements, under the policy of the CIERMag to keep the whole coding in VHDL. Furthermore was implemented an interface to communicate with the Nios II processor to enable system configuration and data transfer through a software running on the processor. The core was projected to be applied with focus on the utilization of low FPGA logical resources with the availability of a high data transfer rate. It will be used in a digital spectrometer under development at the CIERMag. The Quartus II platform, supplied by Altera was used as the development tool. The tests on board where carried out on a DE3-150 development kit from Terasic, which has an FPGA Stratix III also from Altera. In order to test and validate the system, a software for the Nios II processor was developed, able to send and receive data via IPC and with intelligence to answer ARP and PING types requests. The developed Gigabit Ethernet subsystem is now part of the running version of the CIERMag Digital MR Spectrometer.

Neste trabalho, é apresentado o desenvolvimento de um IP de rede Ethernet com interface para o barramento Avalon para utilização em conjunto com o processador Nios II da Altera. O IPC foi adaptado do projeto Ethernet_tri_mode, e é capaz de transferir dados a velocidades de 1000, 100 e 10 Mbps. O desenvolvimento envolveu a adaptação do código para atingir os requisitos do projeto, feito segundo as diretrizes do CIERMag de manter todo o código em VHDL. Além disso, foi implementada uma interface de comunicação com o processador Nios II para tornar possível a configuração do sistema, bem como a transferência de dados através de um software sendo executado no processador. O IPC Ethernet foi projetado para ser aplicado no espectrômetro digital em desenvolvimento pelo CIERMag e teve como compromissos a baixa utilização de recursos lógicos do FPGA e, ao mesmo tempo, a disponibilização de uma alta taxa de transferência de dados para o espectrômetro. Como ferramenta de desenvolvimento, foi utilizada a plataforma Quartus II cujo fornecedor é a Altera. Já os testes em placa foram realizados em um kit de desenvolvimento DE3-150 da Terasic, o qual utiliza uma FPGA Stratix III, também da Altera. Com o intuito de testar e validar o sistema, foi desenvolvido um software para o processador Nios II capaz de receber e enviar dados através do IPC e com inteligência para responder pedidos do tipo ARP e PING. O subsistema de Gigabit Ethernet desenvolvido aqui já incorpora a versão corrente do Espectrômetro Digital de RM do CIERMag. / In this work we expose the implementation of an Ethernet network core which interfaces to Avalon bus used along with the Nios II Altera processor. This core was adapted from the Ethernet_tri_mode project. It can transfer data at rates of 1000, 100 and 10 Mbps. The development involved the adaptation of the code to fullfil the project requirements, under the policy of the CIERMag to keep the whole coding in VHDL. Furthermore was implemented an interface to communicate with the Nios II processor to enable system configuration and data transfer through a software running on the processor. The core was projected to be applied with focus on the utilization of low FPGA logical resources with the availability of a high data transfer rate. It will be used in a digital spectrometer under development at the CIERMag. The Quartus II platform, supplied by Altera was used as the development tool. The tests on board where carried out on a DE3-150 development kit from Terasic, which has an FPGA Stratix III also from Altera. In order to test and validate the system, a software for the Nios II processor was developed, able to send and receive data via IPC and with intelligence to answer ARP and PING types requests. The developed Gigabit Ethernet subsystem is now part of the running version of the CIERMag Digital MR Spectrometer.

[pt] O objetivo desta dissertação consiste no desenvolvimento e na realização de um analisador de redes e elementos de redes na taxa de 1 Gbps. A tecnologia de lógica programável (FPGA) é utilizada através de uma placa de desenvolvimento ativada por ferramentas computacionais dedicadas a esta aplicação. O módulo realizado é utilizado para caracterizar uma rede e alguns elementos de rede em função da taxa máxima de transmissão de pacotes, número de pacotes perdidos e retardo. Uma comparação entre os resultados fornecidos pelo módulo desenvolvido e um equipamento comercial é apresentada e comentada. Finalmente, as principais vantagens da proposta desta dissertação são destacadas. / [en] The main purpose of this dissertation is the development and realization of a Gigabit Ethernet network element analyzer. The FPGA technology is employed through a development board, activated by dedicated software tools. The prototype realized is employed to describe a network and network elements by maximum transmission capacity, frame loss and delay. A comparative analysis between this prototype and a commercial equipment is performed. Finally, the main advantages of this dissertation will be highlighted.

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur Rechnernetze und verteilte Systeme der Fakultaet fuer Informatik der TU Chemnitz. Technologieentwicklungen bei 10 Gigabit Ethernet (10GE) Erweiterung des Ethernet-Schichtenmodells bei 10 Gigabit Ethernet Uebertragungsverfahren auf verschiedenen Glasfasertypen bei verschiedenen Wellenlaengen

Analog-to-Digital (ADC) converters have been an essential building block of electronic design for years. As ADC components get faster, new data interfaces are required in order to keep up with the faster data rates while providing very high data integrity. The objective of this project was to design an inter-IC ADC interface for converters with data bandwidths as high as 56 Gigabytes per second. The main goal for this project was to create a mechanism for interfacing a general-purpose high-speed ADC integrated circuit with an FPGA. This will enable applications that can benefit from the reprogrammability offered by FPGAs as well as those that could not justify a monolithic integrated solution for cost reasons. The interface presented is based on the physical layer of the IEEE 10GBASE-KR specification for 10 Gigabit Ethernet (10GE). Leveraging this specification provides significant benefits as it defines most of the services required by the interface, such as effcient encoding and forward error correction. Furthermore, using an interface as widely used as 10GBASE-KR leverages significant validation work as well as widespread support in mainstream FPGAs and by IP providers. The report will provide an analysis of the requirements of the ADC interface and a description of the architecture proposed. One key aspect of the design of the system was the analysis of the e ects of random bit errors in the channel and how to deal with them while making a robust interface. The causes of error are described and the critical sections of the system were simulated to validate the choice of Forward Error Correction solution. Finally, the report describes the working prototype system built in an FPGA board and provides a description of the performance achieved. / text

10 Gigabit Ethernet (GbE) demands faster optical sources to support high modulation rates. At the same time, the allowable margin in the 10 GbE link power budget is decreasing. This means that a 10 GbE system is unable to support as many tight bends, and it is more difficult to avoid the costly downtime that results when the allowable margin is exceeded. The recent introduction of bend-optimized (BO) multimode fiber (MMF) provides a clear solution. 850 nm vertical cavity surface emitting lasers (VCSELs) and MMFs have long been the most cost effective choice for short reach premise applications. As will be shown, the combination of BO-MMF with VCSELs is even more attractive.Historically, MMF systems operating at low bit rates of 10-100 Mbps used light-emitting diodes (LED) sources, which launch nearly equal power into every fibermode. This launch is approximated by the overfilled launch (OFL), which is still used to characterize the core diameter and numerical aperture of MMF. Unlike LEDs, VCSELs typically underfill the fiber core and are better represented by an encircled flux launch (EFL). Using OFL to evaluate a VCSEL-based MMF system could therefore produce inaccurate and misleading results. A recent study [1] characterized the macrobend loss of MMF with overfilled and restricted mode offset launch conditions. In this study, the MMFs performance with an EFL is evaluated, which is a more relevant launch condition for laser transmission. The impact of both launch conditions, OFL and EFL, on MMF performance is studied and compared.We characterize macrobend losses at small bend radii and their impact on thebandwidth for both standard 50/125 um MMF and a newly introduced BO-MMF.In addition, the 10 GbE link performance is also evaluated using the IEEE link model P802.3ae3.The simulation results illustrate that both macrobend loss and bandwidth are vital to the overall optical link performance. The 10 GbE link performance of the standard fiber deteriorates with macrobends, while the bend-optimized fiber is insensitive to the deployment conditions.

No description available.

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur Rechnernetze und verteilte Systeme der Fakultaet fuer Informatik der TU Chemnitz. Technologieentwicklungen bei 10 Gigabit Ethernet (10GE) Erweiterung des Ethernet-Schichtenmodells bei 10 Gigabit Ethernet Uebertragungsverfahren auf verschiedenen Glasfasertypen bei verschiedenen Wellenlaengen

[pt] Este trabalho tem como objetivo avaliar a viabilidade técnica para fabricação de placas de circuito impresso de múltiplas camadas com espessuras reduzidas mantendo a integridade dos sinais que se propagam em conexões inter- chip, nas taxas de transmissão de 1Gb/s e 10Gb/s para aplicações em redes de comunicações nos padrões 1GB Ethernet e 10GB Ethernet. A avaliação inclui o projeto de uma placa de 6 camadas de planos condutores, com espessura total de 1,29mm. A placa desenvolvida contém linhas de transmissão, vias e curvas, microcapacitores , microresistores e conectores I/O adequados para a faixa de freqüência em questão. / [en] The main purpose of this work is to evaluate the technical reliability to fabricate a Printed circuit board (PCB) with reduced thickness multilayer keeping signal Integrity on inter-chip connections in 1Gb/s and 10Gb/s (1GB Ethernet and 10GB Ethernet network communications). This evaluation includes the development of a PCB project with 06 layers and 1,29mm thickness. The PCB contains several transmission lines, vias, bends, microcapacitors, microresistors, connectors (I/O) suitable to this frequency band.