Al–O monolayers embedded in ultrathin SiO₂ were shown previously to contain Al-induced acceptor states, which capture electrons from adjacent silicon wafers and generate a negative fixed charge that enables efficient Si-surface passivation. Here, we show that this surface passivation is just in part attributed to field-effect passivation, since the electrically active interface trap density Dit itself at the Si/SiO₂ interface is reduced by the presence of the acceptor states. For sufficiently thin tunnel-SiO₂ films between the Si-surface and the Al–O monolayers, Dit is reduced by more than one order of magnitude. This is attributed to an interface defect deactivation mechanism that involves the discharge of the singly-occupied dangling bonds (Pb0 defects) into the acceptor states, so that Shockley-Read-Hall-recombination is drastically reduced. We demonstrate that the combined electronic and field-effect passivation allows for minority carrier lifetimes in excess of 1 ms on n-type Si and that additional H₂-passivation is not able to improve that lifetime significantly.

So far, only CMOS compatible and scalable hafnia-zirconia (HZO) based ferroelectric (FE) n-FeFETs have been reported. To enable the full ferroelectric hierarchy [1] both p- and n-type devices should be available. Here we report a p-FeFET with a large memory window (MW) for the first time. Moreover, we propose different integration schemes comprising structures with and without internal gate resulting in metal-FE-insulator-Si (MFIS) and metal-FE-metal-insulator-Si (MFMIS) devices which could be used to tackle the problem of interface (IF) degradation and possibly decrease the power consumption of the devices.

Here, silicon oxide was formed in a U-shaped trench of a power metal-oxide semiconductor field-effect transistor device by various processes. One SiO₂ formation process was performed in multiple steps to create a low-defect Si-SiO₂ interface, where first a thin initial oxide was grown by thermal oxidation followed by the deposition of a much thicker oxide layer by chemical vapor deposition (CVD). In a second novel approach, silicon nitride CVD was combined with radical oxidation to form silicon oxide in a stepwise sequence. The resulting stack of silicon oxide films was then annealed at temperatures between 1000 and 1100 °C. All processes were executed in an industrial environment using 200 mm-diameter (100)-oriented silicon wafers. The goal was to optimize the trade-off between wafer uniformity and conformality of the trenches. The thickness of the resulting silicon oxide films was determined by ellipsometry of the wafer surface and by scanning electron microscopy of the trench cross sections. The insulation properties such as gate leakage and electrical breakdown were characterized by current–voltage profiling. The electrical breakdown was found to be highest for films treated with rapid thermal processing. The films fabricated via the introduced sequential process exhibited a breakdown behavior comparable to films deposited by the common low-pressure CVD technique, while the leakage current at electric fields higher than 5 MV/cm was significantly lower.