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The increasing application of Neural Networks (NNs) in various fields has heightened the demand for specialized hardware to enhance performance and efficiency. Field-Programmable Gate Arrays (FPGAs) have emerged as a popular choice for implementing NN accelerators due to their flexibility, high performance, and ability to be customized for specific NN architectures. However, the trend of outsourcing Integrated Circuit (IC) design to third parties has introduced new security vulnerabilities, particularly in the form of Hardware Trojans (HTs). These malicious alterations can severely compromise the integrity and functionality of NN accelerators. Building upon this, this study investigates a novel type of HT that degrades the accuracy of Convolutional Neural Network (CNN) accelerators over time. Two variants of the attack are presented: Gradually Degrading Accuracy Trojan (GDAT) and Suddenly Degrading Accuracy Trojan (SDAT), implemented in various components of the CNN accelerator. The approach presented leverages a sensitivity analysis to identify the most impactful targets for the trojan and evaluates the attack’s effectiveness based on stealthiness, hardware overhead, and impact on accuracy.  The overhead of the attacks was found to be competitive when compared to other trojans, and has the potential to undermine trust and cause economic damages if deployed. Out of the components targeted, the memory component for the feature maps was identified as the most vulnerable to this attack, closely followed by the bias memory component. The feature map trojans resulted in a significant accuracy degradation of 78.16% with a 0.15% and 0.29% increase in Look-Up-Table (LUT) utilization for the SDAT and GDAT variants, respectively. In comparison, the bias trojans caused an accuracy degradation of 63.33% with a LUT utilization increase of 0.20% and 0.33% for the respective trojans. The power consumption overhead was consistent at 0.16% for both the attacks and trojan versions.

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Avec la mondialisation du marché des semi-conducteurs, l'intégrité des circuits intégrés (CI) est devenue préoccupante... On distingue deux menaces principales : les chevaux de Troie matériel (CTM) et les contrefaçons. La principale limite des méthodes de vérification de l’intégrité proposées jusqu'à maintenant est le biais induit par les variations des procédés de fabrication. Cette thèse a pour but de proposer une méthode de détection embarquée de détection de CTM et de contrefaçons. À cette fin, une caractérisation de l'impact des modifications malveillantes sur un réseau de capteurs embarqué a été effectuée. L'addition malicieuse de portes logiques (CTM) ou la modification de l'implémentation du circuit (contrefaçons) modifie la distribution de la tension à la l'intérieur du circuit. Une nouvelle approche est proposée afin d'éliminer l'influence des variations des procédés. Nous posons que pour des raisons de cout et de faisabilité, une infection est faite à l'échelle d'un lot de production. Un nouveau modèle de variation de performance temporelle des structures CMOS en condition de design réel est introduit. Ce modèle est utilisé pour créer des signatures de lots indépendantes des variations de procédé et utilisé pour définir une méthode permettant de détecter les CTMs et les contrefaçons.Enfin nous proposons un nouveau distingueur permettant de déterminer, avec un taux de succès de 100%, si un CI est infecté ou non. Ce distingueur permet de placer automatiquement un seuil de décision adapté à la qualité des mesures et aux variations de procédés. Les résultats ont été expérimentalement validés sur un lot de cartes de prototypage FPGA. / Due to the trend to outsourcing semiconductor manufacturing, the integrity of integrated circuits (ICs) became a hot topic. The two mains threats are hardware Trojan (HT) and counterfeits. The main limit of the integrity verification techniques proposed so far is that the bias, induced by the process variations, restricts their efficiency and practicality. In this thesis we aim to detect HTs and counterfeits in a fully embedded way. To that end we first characterize the impact of malicious insertions on a network of sensors. The measurements are done using a network of Ring oscillators. The malicious adding of logic gates (Hardware Trojan) or the modification of the implementation of a different design (counterfeits) will modify the voltage distribution within the IC.Based on these results we present an on-chip detection method for verifying the integrity of ICs. We propose a novel approach which in practice eliminates this limit of process variation bias by making the assumption that IC infection is done at a lot level. We introduce a new variation model for the performance of CMOS structures. This model is used to create signatures of lots which are independent of the process variations. A new distinguisher has been proposed to evaluate whether an IC is infected. This distinguisher allows automatically setting a decision making threshold that is adapted to the measurement quality and the process variation. The goal of this distinguisher is to reach a 100\% success rate within the set of covered HTs family. All the results have been experientially validated and characterized on a set of FPGA prototyping boards.

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