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With the increase in globalization of Integrated Circuit (IC) design and production, hardware trojans have become a serious threat to manufacturers as well as consumers. These trojans could be intensionally or accidentally embedded in ICs to make a system vulnerable to hardware attacks. The implementation of critical applications using ICs makes the effect of trojans an even more serious problem. Moreover, the presence of untrusted foundries and designs cannot be eliminated since the need for ICs is growing exponentially and the use of third party software tools to design the circuits is now common. In addition if a trusted foundry for fabrication has to be developed, it involves a huge investment. Therefore, hardware trojan detection techniques are essential. Very Large Scale Integration (VLSI) system designers must now consider the security of a system against internal and external hardware attacks. Many hardware attacks rely on system vulnerabilities. Moreover, an attacker may rely on deprocessing and reverse engineering to study the internal structure of a system to reveal the system functionality in order to steal secret keys or copy the system. Thus hardware security is a major challenge for the hardware industry. Many hardware attack mitigation techniques have been proposed to help system designers build secure systems that can resist hardware attacks during the design stage, while others protect the system against attacks during operation. In this dissertation, the idea of quantifying hardware attacks, hardware trojans, and hardware trojan detection techniques is introduced. We analyze and classify hardware attacks into risk levels based on three dimensions Accessibility/Resources/Time (ART). We propose a methodology and algorithms to aid the attacker/defender to select/predict the hardware attacks that could use/threaten the system based on the attacker/defender capabilities. Because many of these attacks depends on hardware trojans embedded in the system, we propose a comprehensive hardware trojan classification based on hardware trojan attributes divided into eight categories. An adjacency matrix is generated based on the internal relationship between the attributes within a category and external relationship between attributes in different categories. We propose a methodology to generate a trojan life-cycle based on attributes determined by an attacker/defender to build/investigate a trojan. Trojan identification and severity are studied to provide a systematic way to compare trojans. Trojan detection identification and coverage is also studied to provide a systematic way to compare detection techniques and measure their e effectiveness related to trojan severity. We classify hardware attack mitigation techniques based on the hardware attack risk levels. Finally, we match these techniques to the attacks the could countermeasure to help defenders select appropriate techniques to protect their systems against potential hardware attacks. / Graduate / 0544 / 0984 / samerm@uvic.ca

Traditionally, cryptographic algorithms are designed under the so-called black-box model, which considers adversaries that receive black-box access to the hardware implementation. Although a "black-box" treatment covers a wide range of attacks, it fails to capture reality adequately, as real-world adversaries can exploit physical properties of the implementation, mounting attacks that enable unexpected, non-black-box access, to the components of the cryptographic system. This type of attacks is widely known as physical attacks, and has proven to be a significant threat to the real-world security of cryptographic systems. The present dissertation is (partially) dealing with the problem of protecting cryptographic memory against physical attacks, via the use of non-malleable codes, which is a notion introduced in a preceding work, aiming to provide privacy of the encoded data, in the presence of adversarial faults. In the present thesis we improve the current state-of-the-art on non-malleable codes and we provide practical solutions for protecting real-world cryptographic implementations against physical attacks. Our study is primarily focusing on the following adversarial models: (i) the extensively studied split-state model, which assumes that private memory splits into two parts, and the adversary tampers with each part, independently, and (ii) the model of partial functions, which is introduced by the current thesis, and models adversaries that access arbitrary subsets of codeword locations, with bounded cardinality. Our study is comprehensive, covering one-time and continuous, attacks, while for the case of partial functions, we manage to achieve a stronger notion of security, that we call non-malleability with manipulation detection, that in addition to privacy, it also guarantees integrity of the private data. It should be noted that, our techniques are also useful for the problem of establishing, private, keyless communication, over adversarial communication channels. Besides physical attacks, another important concern related to cryptographic hardware security, is that the hardware fabrication process is assumed to be trusted. In reality though, when aiming to minimize the production costs, or whenever access to leading-edge manufacturing facilities is required, the fabrication process requires the involvement of several, potentially malicious, facilities. Consequently, cryptographic hardware is susceptible to the so-called hardware Trojans, which are hardware components that are maliciously implanted to the original circuitry, having as a purpose to alter the device's functionality, while remaining undetected. Part of the present dissertation, deals with the problem of protecting cryptographic hardware against Trojan injection attacks, by (i) proposing a formal model for assessing the security of cryptographic hardware, whose production has been partially outsourced to a set of untrusted, and possibly malicious, manufacturers, and (ii) by proposing a compiler that transforms any cryptographic circuit, into another, that can be securely outsourced.

Hardware trojans pose a serious threat to trusted computing. However, hardware trojan detection methods are both numerous and onerous, making hardware trojan detection a difficult and time-consuming procedure. This thesis introduces the IP Assurance Framework, which drastically improves the time it takes design teams to test for hardware trojans. The IP Assurance Framework is implemented in two ways: The first method, Physical Assurance, compares instantiated IP blocks to a golden model via physical-level comparisons, while the second method, Functional Assurance, compares IP to a golden model using logical-level comparisons. Both methods are demonstrated to distinguish between tampered and untampered IP blocks, with a tolerable effect on IP timing and area.

No description available.

Η επιστήμη της τεχνολογίας αυξάνεται ραγδαία μέρα με τη μέρα. Δυστυχώς όμως όλες αυτές οι νέες τεχνολογικές τάσεις μπορεί να κρύβουν δυσάρεστες «εκπλήξεις». Τα τελευταία χρόνια οι ασύρματες επικοινωνίες έχουν γίνει ένα πολύ σημαντικό κομμάτι της καθημερινότητάς μας. Εμπιστευόμαστε τις ασύρματες συσκευές μας και τις εταιρίες που τις παρέχουν. Ωστόσο, ερωτήματα όπως πόσο ασφαλείς μπορεί να είναι οι συσκευές μας ή οι ασύρματες επικοινωνίες μας δημιουργούνται κάθε μέρα. Παράλληλα με αυτά τα ερωτήματα, εμφανίζονται και τα Hardware Trojans. Τα Hardware Trojans είναι μέρος αυτών των καινούριων τάσεων και αποτελούν ένα πολύ σοβαρό πρόβλημα στο πεδίο των ολοκληρωμένων κυκλωμάτων. Μέχρι σήμερα έχουν γίνει ποικίλες μελέτες, χρησιμοποιώντας διαφορετικές στρατηγικές, Trojans και μεθόδους ανίχνευσης. Στη συγκεκριμένη διπλωματική εργασία παρουσιάζουμε ένα σύστημα ανίχνευσης για Hardware Trojans σε ολοκληρωμένα κυκλώματα ασύρματης κρυπτογράφησης (wireless cryptographic integrated circuit). Περιγράφεται η διαρροή των μυστικών πληροφοριών μέσω ασύρματης επικοινωνίας, χρησιμοποιώντας την τεχνική των ολοκληρωμένων κυκλωμάτων μικτού σήματος (mixed-signal integrated circuits). Δημιουργήθηκαν δύο διαφορετικά Hardware Trojans, τα οποία εισήχθησαν στο αρχικό μας σύστημα, τα οποία βέβαια δεν αλλάζουν τη λειτουργικότητά του. Παρ’ όλ’ αυτά, μπορούν να διαρρεύσουν μυστικές πληροφορίες του συστήματος. Παρουσιάζεται λοιπόν πως είναι δυνατόν να ανιχνευτεί ένα Trojan επιτυχώς μέσω διαφορετικών στατιστικών μετρήσεων που αφορούν τη συχνότητα και το πλάτος του ασύρματου σήματος μετάδοσης. / Technology grows so rapidly day by day. Unfortunately, all these new technological trends may hide unpleasant “surprises”. In recent years wireless communications have become an important part of our everyday life. We rely on our wireless devices and the companies who provide them. However, questions like how safe can our devices be or how secure can our wireless communications be, rise up almost every day. In parallel with these questions, the appearance of Hardware Trojans rise up too. Hardware Trojans are part of these new trends and they have become a serious issue in the field of integrated circuits. Various studies have been done till today, using different strategies, Trojans and detection methods. At this dissertation it is presented a Hardware Trojan detection framework in wireless cryptographic integrated circuit. Τhe leak of secret information through wireless communication is described, using the technic of mixed-signal integrated circuits. There are two Hardware Trojans created and inserted to the original system, which do not change the functionality of the system, but can leak secret information from it. It is presented how a Trojan can be successfully detected through different statistic measurements which are related to the frequency and amplitude of the wireless transmission signal.

Security assurance in a computer system can be viewed as distinguishing between self and non-self. Artificial Immune Systems (AIS) are a class of machine learning (ML) techniques inspired by the behavior of innate biological immune systems, which have evolved to accurately classify self-behavior from non-self-behavior. This work aims to leverage AIS-based ML techniques for identifying certain behavioral traits in high level hardware descriptions, including unsafe or undesirable behaviors, whether such behavior exists due to human error during development or due to intentional, malicious circuit modifications, known as hardware Trojans, without the need fora golden reference model. We explore the use of Negative Selection and Clonal Selection Algorithms, which have historically been applied to malware detection on software binaries, to detect potentially unsafe or malicious behavior in hardware. We present a software tool which analyzes Trojan-inserted benchmarks, extracts their control and data-flow graphs (CDFGs), and uses this to train an AIS behavior model, against which new hardware descriptions may be tested.

Microcontrollers and integrated circuits in general have become ubiquitous in the world today. All aspects of our lives depend on them from driving to work, to calling our friends, to checking our bank account balance. People who would do harm to individuals, corporations and nation states are aware of this and for that reason they seek to find or create and exploit vulnerabilities in integrated circuits. This dissertation contains three papers dealing with these types of vulnerabilities. The first paper talks about a vulnerability that was found on a microcontroller, which is a type of integrated circuit. The final two papers deal with hardware trojans. Hardware trojans are purposely added to the design of an integrated circuit in secret so that the manufacturer doesn’t know about it. They are used to damage the integrated circuit, leak confidential information, or in other ways alter the circuit. Hardware trojans are a major concern for anyone using integrated circuits because an attacker can alter a circuit in almost any way if they are successful in inserting one. A known method to prevent hardware trojan insertion is discussed and a type of circuit for which this method does not work is revealed. The discussion of hardware trojans is concluded with a new way to detect them before the integrated circuit is manufactured. Modern deep learning models are used to detect the portions of the hardware trojan called triggers that activate them.

abstract: Power management circuits are employed in most electronic integrated systems, including applications for automotive, IoT, and smart wearables. Oftentimes, these power management circuits become a single point of system failure, and since they are present in most modern electronic devices, they become a target for hardware security attacks. Digital circuits are typically more prone to security attacks compared to analog circuits, but malfunctions in digital circuitry can affect the analog performance/parameters of power management circuits. This research studies the effect that these hacks will have on the analog performance of power circuits, specifically linear and switching power regulators/converters. Apart from security attacks, these circuits suffer from performance degradations due to temperature, aging, and load stress. Power management circuits usually consist of regulators or converters that regulate the load’s voltage supply by employing a feedback loop, and the stability of the feedback loop is a critical parameter in the system design. Oftentimes, the passive components employed in these circuits shift in value over varying conditions and may cause instability within the power converter. Therefore, variations in the passive components, as well as malicious hardware security attacks, can degrade regulator performance and affect the system’s stability. The traditional ways of detecting phase margin, which indicates system stability, employ techniques that require the converter to be in open loop, and hence can’t be used while the system is deployed in-the-field under normal operation. Aging of components and security attacks may occur after the power management systems have completed post-production test and have been deployed, and they may not cause catastrophic failure of the system, hence making them difficult to detect. These two issues of component variations and security attacks can be detected during normal operation over the product lifetime, if the frequency response of the power converter can be monitored in-situ and in-field. This work presents a method to monitor the phase margin (stability) of a power converter without affecting its normal mode of operation by injecting a white noise/ pseudo random binary sequence (PRBS). Furthermore, this work investigates the analog performance parameters, including phase margin, that are affected by various digital hacks on the control circuitry associated with power converters. A case study of potential hardware attacks is completed for a linear low-dropout regulator (LDO). / Dissertation/Thesis / Masters Thesis Electrical Engineering 2019