The fusion of voice and data applications, along with the demand for high data-rate applications such as video-on-demand, is making radio frequency (RF) spectrum an increasingly expensive commodity for current and future communications. Although bandwidth-efficient digital modulation alleviates part of the problem by requiring a minimal use of spectral resources, they put an extra design burden on RF engineers. RF transmitters and power amplifiers account for more than half the total maintenance cost of a base-station, while occupying nearly the same portion of space. Therefore, power amplifiers become a bottleneck for digital systems in terms of space and power consumption. However, power-efficient use of the amplifiers, although desirable, is extremely detrimental to end-to-end performance due to the very high peak-to-average power ratios of modulations that are used today. In order to reduce distortion while maintaining high power conversion efficiency in a power amplifier, linearization schemes are needed. In addition, significant frequency-dependent Memory Effects result in high power amplifiers operating on wideband signals. Therefore, these effects need to be considered during any attempt to minimize amplifier distortion. In this thesis, we present two schemes to cancel nonlinear distortion of a power amplifier, along with its memory effects and results for one of the schemes. The results highlight the fact that in the presence of significant memory effects, cancellation of these effects is necessary to achieve reasonable improvement in performance through linearization. We focus on predistortive schemes due to their digital- friendly structure and simple implementation. The operating environment consists of a multi-carrier W-CDMA signal. All of the studies are performed using numerical simulation on MATLAB and Agilent's Advanced Design System (ADS). / Master of Science

This dissertation studies the design of an efficient adaptive digital baseband predistorter for modern cellular handsets that combines low power consumption, low implementation complexity, and high performance. The proposed enhancements are optimized for hardware implementation. We first present a thorough study of the optimal spacing of linearly-interpolated lookup table predistorters supported by theoretical calculations and extensive simulations. A constant-SNR compander that increases the predistorter's supported input dynamic range is derived. A corresponding low-complexity approximation that lends itself to efficient hardware design is also implemented in VHDL and synthesized with the Synopsys Design Compiler. This dissertation also proposes an LMS-based predistorter adaptation that is optimized for hardware implementation and compares the effectiveness of the direct and indirect learning architectures. A novel predistorter design with quadrature imbalance correction capability is developed and a corresponding adaptation scheme is proposed. This robust predistorter configuration is designed by combining linearization and I/Q imbalance correction into a single function with the same computational complexity as the widespread complex-gain predistorter.