The architecture of virtual machine (VM) interpreters has long been a subject of researchand discussion. The initial trend of stack-based interpreters was shortly thereafterchallenged by research showing the performance advantages of virtual register machines. Despite this, many VM interpreters are still stack-based, with some notable exceptions, like Lua, Android Runtime, and its predecessor Dalvik. A register architecture isusually associated with greater overhead from instruction dispatch, and to some extent, instruction decoding. By designing, and implementing a novel technique that replaces the conventional way of decoding instructions, this thesis attempts to reduce that overhead. More specifically, a VM interpreter is developed as an artifact of design-science research. The novel technique is then evaluated through benchmarking in various configurations. As the results indicate, however, using this technique showed no performance advantage, as the resulting machine instructions are exactly the same after compiler optimization. This suggests that there is no apparent decoding overhead to begin with. As a result, register-based VMs seem to not suffer from any dispatch related overhead, other than the fact that there are more operands per instruction to access. Source code is available on GitHub, at https://github.com/kaspr61/RackVM.