NDLTD Global ETD Search
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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 31 to 40 of 7682 (0.054 seconds)
31

"On stochastic modelling of very large scale integrated circuits : an investigation into the timing behaviour of microelectronic systems" /

Bishop, Gregory Raymond H. January 1993 (has links) (PDF)
Thesis (Ph. D.)--University of Adelaide, Faculty of Engineering, 1994? / Includes bibliographical references (leaves 302-320).
Integrated circuits
32

Macromodeling and simulation of high-performance mixed Analog/Digital circuits /

Chang, Yu-Hsu Henry. January 1994 (has links)
Thesis (Ph. D.)--University of Washington, 1994. / Vita. Includes bibliographical references (leaves [93]-98).
Integrated circuits
33

A formal model for behavioral test generation /

Cho, Chang H., January 1994 (has links)
Thesis (Ph. D.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 159-163). Also available via the Internet.
Integrated circuits
34

TENOR : an ATPG for transition faults in combinational circuits /

Tyagi, Dhawal, January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 70-72). Also available via the Internet.
Integrated circuits
35

Setting CMOS environment for VLSI design

Chung, Chih-Ping. January 1989 (has links)
Thesis (M.S.)--Ohio University, November, 1989. / Title from PDF t.p.
Integrated circuits
36

VLSI implementation of control section of overlapped 3-bit scanning 64-bit multiplier

Montalvo Ramirez, Luis Anibal. January 1986 (has links)
Thesis (M.S.)--Ohio University, August, 1986. / Title from PDF t.p.
Integrated circuits
37

Global routing and pin assignment for multi-layer chip-level layout /

Liu, Le-Chin Eugene. January 1997 (has links)
Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [78]-83).
Integrated circuits
38

Architectural retiming : a technique for optimizing latency-constrained circuits /

Hassoun, Soha M. N. January 1997 (has links)
Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [151]-154).
Integrated circuits
39

A built-in self-test PLA generator /

Dhawan, Sanjay, January 1991 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaves 87-90). Also available via the Internet.
Integrated circuits
40

Modeling of lossy multiconductor transmission lines for the design of high-speed IC interconnects /

You, Hong. January 1990 (has links)
Thesis (Ph. D.)--University of Washington, 1990. / Vita. Includes bibliographical references (leaves [111]-115).
Integrated circuits

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