Global ETD Search

151	Analysis of fault coverage masking in built-in self-test schemes Cotsapas, Nicos. January 1985 (has links) No description available. Integrated circuits -- Testing.
152	Organic film and contaminant removal from surfaces in the manufacture of integrated circuits Chavez, Kristi Lynn 12 1900 (has links) No description available. Integrated circuits Cleaning.
153	Test support processor for enhanced testability of high performance integrated circuits Zhou, Qing 08 1900 (has links) No description available. Integrated circuits Testing
154	Analog four-quadrant multiplier using NMOS integrated circuit technology Peña Finol, Jesús Salvador 08 1900 (has links) No description available. Integrated circuits Analog multipliers
155	Signature based testing of analog and RF circuits Voorakaranam, Ramakrishna 05 1900 (has links) No description available. Integrated circuits Testing
156	Study on thermally reworkable underfills for flip chip, BGA, and CSP applications Wang, Lejun 05 1900 (has links) No description available. Integrated circuits Electronic packaging
157	Enhancement of flow time and adhesion of high-performance underfill encapsulants for flip-chip applications Vincent, Michael Brien 12 1900 (has links) No description available.
158	An assessment of dual-rail encoded on-line test methodologies and their impact on ASIC/FPGA design Thulborn, David January 1997 (has links) The testing of fabricated Integrated Circuits (IC's) is of great concern to production engineers and circuit designers alike. With the complexity of Very Large Scale Integrated (VLSI) circuits increasing every year, the problem of testing the fabricated designs is becoming acute. Several methods for reducing the burden of IC testing have been incorporated into the designs being tested thus giving rise to the phrase Design For Test (DFT). This thesis aims to understand how dual rail encoding of digital data can affect the different characteristics of electronic circuits. More specifically, it investigates a novel on-line test methodology called IFIS (If it Fails, It Stops), and its impact upon the design and implementation of electronic circuits intended for Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) technologies. The first two studies investigate the characteristics of the IFIS methodology to determine the most efficient and effective encoding scheme, protocol rules and feedback structures required for data processing. The third study investigates a series of possible improvements to the design of IFIS cells and determines the most efficient method of designing cells using the IFIS methodology. The final study investigates the feasibility of IFIS using a 'real life' commercial UART re-engineered using the IFIS methodology. The outcome of this work is an identification and characterisation of the factors which influence the performance and implementation cost of the IFIS methodology. 621.3192 Integrated circuits
159	Estimation of Analog Layout Parasitics with Parameterized Polygons Tseng, I-Lun Unknown Date (has links) No description available. 290902 Integrated Circuits
160	Nanometer VLSI placement and optimization for multi-objective design closure Luo, Tao, January 1900 (has links) Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references. Integrated circuits Algorithms.

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