In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.

by Sau-yuen Wong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 77-82). / Acknowledgement --- p.i / Abstract --- p.ii / List of Tables --- p.ii / List of Figures --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Review of Previous Work --- p.4 / Chapter 2.1 --- Optimization of Delay and Layout Design --- p.4 / Chapter 2.2 --- Simulated Annealing --- p.8 / Chapter 3 --- Definition of Circuit Model --- p.12 / Chapter 4 --- Evaluation of Delay --- p.16 / Chapter 4.1 --- RC-tree and Elmore Delay --- p.16 / Chapter 4.2 --- Exponential Decayed Polynomial Function --- p.17 / Chapter 4.3 --- Two-pole Approximation --- p.18 / Chapter 4.4 --- AWE and Adopted Delay Model --- p.19 / Chapter 5 --- Delay Minimization by Simulated Annealing --- p.28 / Chapter 5.1 --- Cost Function --- p.28 / Chapter 5.2 --- Neighbor Moves --- p.30 / Chapter 5.2.1 --- Logical models --- p.31 / Chapter 5.2.2 --- Discretization of Solution Space --- p.32 / Chapter 5.2.3 --- Valid Configurations --- p.35 / Chapter 5.2.4 --- Valid Moves --- p.39 / Chapter 5.2.5 --- Modification to the Newly Generated Graph --- p.41 / Chapter 5.2.6 --- Access to Neighbor configuration --- p.43 / Chapter 5.2.7 --- Reduction of Solution Space --- p.45 / Chapter 5.2.8 --- Correctness of the Algorithm --- p.48 / Chapter 5.2.9 --- Completeness of the Algorithm --- p.49 / Chapter 6 --- Experimental result --- p.56 / Chapter 6.1 --- Optimization of Overall Performance --- p.58 / Chapter 6.2 --- Optimization on Individual Delay --- p.70 / Chapter 7 --- Conclusion --- p.74 / A --- p.76 / Bibliography

by Eva Yuk-Wah Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 88-89). / ACKNOWLEDGEMETS / ABSTRACT / LIST OF FIGURES / LIST OF TABLES / Chapter CHAPTER1 --- INTRODUCTION / Chapter 1.1 --- Motivation --- p.1-1 / Chapter 1.1.1 --- Problems with Synchronous Systems --- p.1-1 / Chapter 1.1.2 --- The Advantages of Self-timed Systems --- p.1-2 / Chapter 1.1.3 --- Self-Timed Cell Library --- p.1-3 / Chapter 1.2 --- Overview of the Thesis --- p.1-5 / Chapter CHAPTER2 --- BACKGROUND / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Models for Asynchronous System --- p.2-2 / Chapter 2.2.1 --- Huffman model --- p.2-2 / Chapter 2.2.2 --- Muller model --- p.2-4 / Chapter 2.3 --- Self-timed System --- p.2-5 / Chapter 2.3.1 --- Definitions and Assumptions --- p.2-6 / Chapter 2.4 --- Design Methodologies --- p.2-8 / Chapter 2.4.1 --- Differential Logic Structure Design Methodology --- p.2-9 / Chapter 2.4.1.1 --- Data Path --- p.2-9 / Chapter 2.4.1.2 --- Control Path --- p.2-10 / Chapter 2.4.2 --- Micropipeline Design Methodology --- p.2-12 / Chapter 2.4.2.1 --- Data Path --- p.2-12 / Chapter 2.4.2.2 --- Control Path --- p.2-13 / Chapter CHAPTER3 --- SELF-TIMED CELL LIBRARY / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Muller C element --- p.3-1 / Chapter 3.3 --- Differential Cascode Voltage Switch Logic Circuits --- p.3-6 / Chapter 3.3.1 --- INVERTER --- p.3-8 / Chapter 3.3.2 --- "AND, OR, NAND, NOR" --- p.3-8 / Chapter 3.3.3 --- "XOR, XNOR" --- p.3-10 / Chapter 3.4 --- Latches --- p.3-11 / Chapter 3.4.1 --- Precharged Latch --- p.3-12 / Chapter 3.4.2 --- Capture and Pass Latch --- p.3-12 / Chapter 3.5 --- Delay Elements --- p.3-13 / Chapter 3.6 --- Discussion --- p.3-15 / Chapter CHAPTER4 --- THE CHARACTERISTICS OF SELF-TIMED CELL LIBRARY / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- The Simulation Characteristics --- p.4-2 / Chapter 4.2.1 --- HSPICE program --- p.4-2 / Chapter 4.2.2 --- Characterization Information and Datasheet terms --- p.4-5 / Chapter 4.2.3 --- Characterization values --- p.4-6 / Chapter 4.3 --- The Experimental Analysis --- p.4-6 / Chapter 4.4 --- Experimental Result and Discussion --- p.4-9 / Chapter 4.4.1 --- Experimental Result --- p.4-9 / Chapter 4.4.2 --- Comparison of the characteristics of C-elements --- p.4-12 / Chapter 4.4.3 --- Comparison of simulation with experimental results --- p.4-13 / Chapter 4.4.4 --- Properties of DCVSL gate --- p.4-14 / Chapter 4.4.5 --- The Characteristics of Delay elements --- p.4-15 / Chapter 4.5 --- CAD Features on Cadence --- p.4-16 / Chapter CHAPTER5 --- DESIGN EXAMPLE: SELF-TIMED MATRIX MULTIPLIER / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- A Matrix Multiplier using DCVSL structure --- p.5-2 / Chapter 5.2.1 --- Structure --- p.5-2 / Chapter 5.2.2 --- Handshaking Control Circuit --- p.5-3 / Chapter 5.2.2.1 --- Handshaking Control Circuit of Pipeline --- p.5-4 / Chapter 5.2.2.2 --- Handshaking Control Circuit of Feedback Path --- p.5-8 / Chapter 5.3 --- A Matrix Multiplier using Micropipeline Structure --- p.5-10 / Chapter 5.3.1 --- Structure --- p.5-10 / Chapter 5.3.2 --- Control Circuit --- p.5-12 / Chapter 5.4 --- Experimental Result --- p.5-13 / Chapter 5.4.1 --- The Matrix Multiplier using DCVSL structure --- p.5-13 / Chapter 5.4.2 --- The Matrix Multiplier using Micropipeline structure --- p.5-16 / Chapter 5.5 --- Comparison of DCVSL structure and Micropipeline structure --- p.5-18 / Chapter CHAPTER6 --- CONCLUSION / Chapter 6.1 --- Achievement --- p.6-1 / Chapter 6.1.1 --- Self-timed Cell Library --- p.6-1 / Chapter 6.1.2 --- Self-timed System Design simplification --- p.6-2 / Chapter 6.1.3 --- Area and Speed --- p.6-3 / Chapter 6.1.4 --- Applications --- p.6-4 / Chapter 6.2 --- Future work --- p.6-6 / Chapter 6.2.1 --- Interface with synthesis tools --- p.6-6 / Chapter 6.2.2 --- Mixed Circuit Design --- p.6-6 / REFERENCES / APPENDICES

by Lam Shiu-chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (leaves 107-113). / Abstracts in English and Chinese. / List of Figures --- p.v / List of Tables --- p.vii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Task Scheduling Problem and Lower Bound --- p.3 / Chapter 1.3 --- Organization of the Thesis --- p.4 / Chapter 2 --- Teamwork-Task Scheduling Problem --- p.5 / Chapter 2.1 --- Problem Statement and Notations --- p.5 / Chapter 2.2 --- Classification of Scheduling --- p.7 / Chapter 2.3 --- Computational Complexity --- p.9 / Chapter 2.4 --- Literature Review --- p.12 / Chapter 2.4.1 --- Unrelated Machines Scheduling Environment --- p.12 / Chapter 2.4.2 --- Multiprocessors Scheduling Problem --- p.13 / Chapter 2.4.3 --- Search Algorithms --- p.14 / Chapter 2.4.4 --- Lower Bounds --- p.15 / Chapter 2.5 --- Summary --- p.17 / Chapter 3 --- Fundamentals of Genetic Algorithms --- p.18 / Chapter 3.1 --- Initial Inspiration --- p.18 / Chapter 3.2 --- An Elementary Genetic Algorithm --- p.20 / Chapter 3.2.1 --- "Genes, Chromosomes and Representations" --- p.20 / Chapter 3.2.2 --- Population Pool --- p.22 / Chapter 3.2.3 --- Evaluation Module --- p.22 / Chapter 3.2.4 --- Reproduction Module --- p.22 / Chapter 3.2.5 --- Genetic Operators: Crossover and Mutation --- p.23 / Chapter 3.2.6 --- Parameters --- p.24 / Chapter 3.3 --- A Brief Note to the Background Theory --- p.25 / Chapter 3.4 --- Key Factors for the Success --- p.27 / Chapter 4 --- Tasks Scheduling using Genetic Algorithms --- p.28 / Chapter 4.1 --- Details of Scheduling Problem --- p.28 / Chapter 4.2 --- Chromosome Coding --- p.32 / Chapter 4.2.1 --- Job Priority Sequence --- p.33 / Chapter 4.2.2 --- Engineer Priority Sequence --- p.33 / Chapter 4.2.3 --- An Example Chromosome Interpretation --- p.34 / Chapter 4.3 --- Fitness Evaluation --- p.37 / Chapter 4.4 --- Parent Selection --- p.38 / Chapter 4.5 --- Genetic Operators and Reproduction --- p.40 / Chapter 4.5.1 --- Job Priority Crossover (JOB-CRX) --- p.40 / Chapter 4.5.2 --- Job Priority Mutation (JOB-MUT) --- p.40 / Chapter 4.5.3 --- Engineer Priority Mutation (ENG-MUT) --- p.42 / Chapter 4.5.4 --- Reproduction: New Population --- p.42 / Chapter 4.6 --- Replacement Strategy --- p.43 / Chapter 4.7 --- The Complete Genetic Algorithm --- p.44 / Chapter 5 --- Lower Bound on Optimal Makespan --- p.46 / Chapter 5.1 --- Introduction --- p.46 / Chapter 5.2 --- Definitions and Assumptions --- p.48 / Chapter 5.2.1 --- Task Graph --- p.48 / Chapter 5.2.2 --- Graph Partitioning --- p.49 / Chapter 5.2.3 --- Activity and Load Density --- p.51 / Chapter 5.2.4 --- Assumptions --- p.52 / Chapter 5.3 --- Concepts of Lower Bound on the Minimal Time (LBMT) --- p.53 / Chapter 5.3.1 --- Previous Bound (LBMTF) --- p.53 / Chapter 5.3.2 --- Bound in other form --- p.54 / Chapter 5.3.3 --- Improved Bound (LBMTJR） --- p.56 / Chapter 5.4 --- Lower bound: Task graph reconstruction + LBMTJR --- p.59 / Chapter 5.4.1 --- Problem reduction and Assumptions --- p.60 / Chapter 5.4.2 --- Scenario I --- p.61 / Chapter 5.4.3 --- Scenario II --- p.63 / Chapter 5.4.4 --- An Example --- p.67 / Chapter 6 --- Computational Results and Discussions --- p.73 / Chapter 6.1 --- Parameterization of the GA --- p.73 / Chapter 6.2 --- Computational Results --- p.75 / Chapter 6.3 --- Performance Evaluation --- p.81 / Chapter 6.3.1 --- Solution Quality --- p.81 / Chapter 6.3.2 --- Computational Complexity --- p.86 / Chapter 6.4 --- Effects of Machines Eligibility --- p.88 / Chapter 6.5 --- Future Direction --- p.90 / Chapter 7 --- Conclusion --- p.92 / Chapter A --- Tasks data of problem sets in section 6.2 --- p.94 / Chapter A.l --- Problem 1: 19 tasks --- p.95 / Chapter A.2 --- Problem 2: 21 tasks --- p.97 / Chapter A.3 --- Problem 3: 19 tasks --- p.99 / Chapter A.4 --- Problem 4: 23 tasks --- p.101 / Chapter A.5 --- Problem 5: 27 tasks --- p.104 / Bibliography --- p.107

Ching Lap Sze. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 69-71). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Shuttle Mask --- p.2 / Chapter 1.2 --- Voltage Island --- p.6 / Chapter 1.3 --- Structure of the Thesis --- p.8 / Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.1.1 --- Problem formulation --- p.10 / Chapter 2.2 --- Slicing Floorplan --- p.10 / Chapter 2.3 --- General Floorplan --- p.11 / Chapter 2.3.1 --- Conflict Graph Approaches --- p.11 / Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14 / Chapter 2.4 --- Grid Packing --- p.15 / Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15 / Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17 / Chapter 3 --- Shuttle Mask Floorplanning --- p.18 / Chapter 3.1 --- Problem Description --- p.18 / Chapter 3.2 --- An Overview --- p.20 / Chapter 3.3 --- Modified α-Restricted Grid --- p.21 / Chapter 3.4 --- Branch and Bound Algorithm --- p.23 / Chapter 3.4.1 --- Feasibility Check --- p.25 / Chapter 3.5 --- Dicing Plan --- p.30 / Chapter 3.6 --- Experimental Result --- p.30 / Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36 / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Problem Definition --- p.36 / Chapter 4.2 --- Dynamic Programming --- p.38 / Chapter 4.2.1 --- Problem Definition --- p.38 / Chapter 4.2.2 --- Algorithm Overview --- p.38 / Chapter 4.2.3 --- Size Reduction --- p.39 / Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40 / Chapter 4.3 --- Quad-tree Approach --- p.41 / Chapter 5 --- Voltage Island Partitioning --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Problem Formulation --- p.45 / Chapter 5.3 --- Methodology --- p.46 / Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47 / Chapter 5.3.2 --- Tree Construction --- p.49 / Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50 / Chapter 5.3.4 --- Tree Refinement --- p.52 / Chapter 5.3.5 --- Solution Legalization --- p.53 / Chapter 5.3.6 --- Time Complexity --- p.54 / Chapter 5.4 --- Direct Method --- p.55 / Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56 / Chapter 5.4.2 --- Time Complexity --- p.58 / Chapter 5.5 --- Experimental Results --- p.59 / Chapter 6 --- Conclusion --- p.66 / Bibliography --- p.69

Law Hoi Ying. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 101-106). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.6 / Chapter 1.3 --- Floorplanning --- p.10 / Chapter 1.3.1 --- Floorplanning Objectives --- p.11 / Chapter 1.3.2 --- Common Approaches --- p.12 / Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14 / Chapter 1.4 --- Motivations and Contributions --- p.15 / Chapter 1.5 --- Organization of the Thesis --- p.17 / Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18 / Chapter 2.1 --- Types of Floorplans --- p.18 / Chapter 2.2 --- Floorplan Representations --- p.20 / Chapter 2.2.1 --- Slicing Floorplan --- p.21 / Chapter 2.2.2 --- Non-slicing Floorplan --- p.22 / Chapter 2.2.3 --- Mosaic Floorplan --- p.30 / Chapter 2.3 --- Summary --- p.35 / Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37 / Chapter 3.1 --- Introduction --- p.37 / Chapter 3.2 --- Problem Formulation --- p.38 / Chapter 3.3 --- Previous Work --- p.38 / Chapter 3.4 --- Summary --- p.42 / Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44 / Chapter 4.1 --- Problem Formulation --- p.44 / Chapter 4.2 --- Previous Work --- p.45 / Chapter 4.2.1 --- Abutment Constraint --- p.45 / Chapter 4.2.2 --- Alignment Constraint --- p.49 / Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52 / Chapter 4.3 --- Summary --- p.53 / Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Problem Formulation --- p.56 / Chapter 5.3 --- Methodology --- p.57 / Chapter 5.3.1 --- Shape Validation --- p.58 / Chapter 5.3.2 --- Bus Ordering --- p.65 / Chapter 5.3.3 --- Floorplan Realization --- p.72 / Chapter 5.3.4 --- Simulated Annealing --- p.73 / Chapter 5.3.5 --- Soft Block Adjustment --- p.75 / Chapter 5.4 --- Experimental Results --- p.75 / Chapter 5.5 --- Summary --- p.77 / Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80 / Chapter 6.1 --- Introduction --- p.80 / Chapter 6.2 --- Problem Formulation --- p.81 / Chapter 6.3 --- The Representation --- p.82 / Chapter 6.3.1 --- Overview --- p.82 / Chapter 6.3.2 --- Review of TCG --- p.83 / Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84 / Chapter 6.3.4 --- Aligning Blocks --- p.85 / Chapter 6.3.5 --- Solution Perturbation --- p.87 / Chapter 6.4 --- Simulated Annealing --- p.92 / Chapter 6.5 --- Soft Block Adjustment --- p.92 / Chapter 6.6 --- Experimental Results --- p.93 / Chapter 6.7 --- Summary --- p.94 / Chapter 6.8 --- Acknowledgement --- p.95 / Chapter 7 --- Conclusion --- p.99 / Bibliography --- p.101

Sze, Chin Ngai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 80-84) and index. / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Curriculum Vitae --- p.iv / List of Figures --- p.ix / List of Tables --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contribution --- p.8 / Chapter 1.3 --- Organization of Dissertation --- p.10 / Chapter 2 --- Definitions and Notations --- p.11 / Chapter 3 --- Literature Review --- p.15 / Chapter 3.1 --- Logic Reconstruction --- p.15 / Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16 / Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17 / Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18 / Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18 / Chapter 3.2.3 --- REWIRE --- p.21 / Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22 / Chapter 3.3 --- Graph-based Alternative Wiring --- p.24 / Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25 / Chapter 4.1 --- Source Node Implication --- p.25 / Chapter 4.1.1 --- Introduction --- p.25 / Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25 / Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29 / Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32 / Chapter 4.2 --- Destination Node Implication --- p.35 / Chapter 4.2.1 --- Introduction --- p.35 / Chapter 4.2.2 --- Destination Node Relationship --- p.35 / Chapter 4.2.3 --- Destination Node Implication-tree --- p.39 / Chapter 4.2.4 --- Selection of Alternative Wire --- p.41 / Chapter 4.3 --- The Algorithm --- p.43 / Chapter 4.3.1 --- IB AW Implementation --- p.43 / Chapter 4.3.2 --- Experimental Results --- p.43 / Chapter 4.4 --- Conclusion --- p.45 / Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47 / Chapter 5.1 --- Introduction --- p.47 / Chapter 5.2 --- Notations and Definitions --- p.48 / Chapter 5.3 --- Alternative Wire Patterns --- p.50 / Chapter 5.4 --- Construction of Minimal Patterns --- p.54 / Chapter 5.4.1 --- Minimality of Patterns --- p.54 / Chapter 5.4.2 --- Minimal Pattern Formation --- p.56 / Chapter 5.4.3 --- Pattern Extraction --- p.61 / Chapter 5.5 --- Experimental Results --- p.63 / Chapter 5.6 --- Conclusion --- p.63 / Chapter 6 --- Logic Optimization by GBAW --- p.66 / Chapter 6.1 --- Introduction --- p.66 / Chapter 6.2 --- Logic Simplification --- p.67 / Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67 / Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68 / Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70 / Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71 / Chapter 6.4 --- GBAW Optimization Algorithm --- p.73 / Chapter 6.5 --- Experimental Results --- p.73 / Chapter 6.6 --- Conclusion --- p.76 / Chapter 7 --- Conclusion --- p.78 / Bibliography --- p.80 / Chapter A --- VLSI Design Cycle --- p.85 / Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87 / Chapter B.1 --- 0-local Pattern --- p.87 / Chapter B.2 --- 1-local Pattern --- p.88 / Chapter B.3 --- 2-local Pattern --- p.89 / Chapter B.4 --- Fanout-reconvergent Pattern --- p.90 / Chapter C --- New Alternative Wire Patterns --- p.91 / Chapter C.1 --- Pattern Cluster C1 --- p.91 / Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91 / Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92 / Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95 / Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95 / Chapter C.2 --- Pattern Cluster C2 --- p.98 / Chapter C.3 --- Pattern Cluster C3 --- p.99 / Chapter C.4 --- Pattern Cluster C4 --- p.104 / Chapter C.5 --- Pattern Cluster C5 --- p.105 / Glossary --- p.106 / Index --- p.108

Ma, Qiang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Floorplanning --- p.2 / Chapter 1.3 --- Motivations --- p.4 / Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5 / Chapter 1.5 --- Problem Formulation --- p.8 / Chapter 1.6 --- Progress on the Problem --- p.10 / Chapter 1.7 --- Contributions --- p.12 / Chapter 1.8 --- Thesis Organization --- p.14 / Chapter 2 --- Literature Review on MSV --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16 / Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16 / Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18 / Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19 / Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20 / Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21 / Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22 / Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22 / Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23 / Chapter 2.4 --- Summary --- p.27 / Chapter 3 --- MSV Driven Floorplanning --- p.29 / Chapter 3.1 --- Introduction --- p.29 / Chapter 3.2 --- Problem Formulation --- p.32 / Chapter 3.3 --- Algorithm Overview --- p.33 / Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33 / Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35 / Chapter 3.4.2 --- Proof of Optimality --- p.36 / Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37 / Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38 / Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39 / Chapter 3.5 --- Simulated Annealing --- p.39 / Chapter 3.5.1 --- Moves --- p.39 / Chapter 3.5.2 --- Cost Function --- p.40 / Chapter 3.6 --- Experimental Results --- p.40 / Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45 / Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46 / Chapter 3.7 --- Summary --- p.46 / Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49 / Chapter 4.1 --- Introduction --- p.49 / Chapter 4.2 --- Problem Formulation --- p.52 / Chapter 4.3 --- Algorithm Overview --- p.56 / Chapter 4.4 --- Voltage Assignment Problem --- p.56 / Chapter 4.4.1 --- Lagrangian Relaxation --- p.58 / Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60 / Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64 / Chapter 4.4.4 --- Solution Transformation --- p.66 / Chapter 4.5 --- Simulated Annealing --- p.69 / Chapter 4.5.1 --- Moves --- p.69 / Chapter 4.5.2 --- Speeding up heuristic --- p.69 / Chapter 4.5.3 --- Cost Function --- p.70 / Chapter 4.5.4 --- Annealing Schedule --- p.71 / Chapter 4.6 --- Experimental Results --- p.71 / Chapter 4.7 --- Summary --- p.72 / Chapter 5 --- Conclusion --- p.76 / Bibliography --- p.80

Jiang, Yan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 87-92). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.14 / Chapter 1.4 --- Organization of the Thesis --- p.15 / Chapter 2 --- Literature Review on BDF --- p.17 / Chapter 2.1 --- Zero-Bend BDF --- p.17 / Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17 / Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20 / Chapter 2.2 --- Two-Bend BDF --- p.22 / Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25 / Chapter 2.3.1 --- Placement Constraints for Bus --- p.26 / Chapter 2.3.2 --- Bus Ordering --- p.28 / Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30 / Chapter 2.5 --- Summary --- p.33 / Chapter 3 --- Fixed-Outline BDF --- p.35 / Chapter 3.1 --- Introduction --- p.35 / Chapter 3.2 --- Problem Formulation --- p.36 / Chapter 3.3 --- The Overview of Our Approach --- p.36 / Chapter 3.4 --- Partitioning --- p.37 / Chapter 3.4.1. --- The Overview of Partitioning --- p.38 / Chapter 3.4.2 --- Building a Hypergraph G --- p.39 / Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43 / Chapter 3.5.1 --- Find Bus Routes --- p.43 / Chapter 3.5.2 --- Realization of Bus Routes --- p.48 / Chapter 3.5.3 --- Details of the Annealing Process --- p.50 / Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52 / Chapter 3.7 --- Bus Layout --- p.52 / Chapter 3.8 --- Experimental Results --- p.56 / Chapter 3.9 --- Summary --- p.61 / Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63 / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Problem Formulation --- p.64 / Chapter 4.3 --- Our Approach --- p.65 / Chapter 4.3.1 --- Bus Routability Checking --- p.67 / Chapter 4.3.2 --- Details of the Annealing Process --- p.79 / Chapter 4.4 --- Experimental Results --- p.79 / Chapter 4.5 --- Summary --- p.82 / Chapter 5 --- Conclusion --- p.85 / Bibliography --- p.92

Includes bibliography.