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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
31

Canal M-APSK não-coerente de bloco : capacidade e proposta de codificação para receptores iterativos / Blockwise noncoherent M-APSK channel: capacity and coding scheme for iterative receivers

Cunha, Daniel Carvalho da 26 May 2006 (has links)
Orientador: Jaime Portugheis / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-06T20:11:55Z (GMT). No. of bitstreams: 1 Cunha_DanielCarvalhoda_D.pdf: 2995961 bytes, checksum: 3bbce0e569994999c363151f6510cef1 (MD5) Previous issue date: 2006 / Resumo: Em varios sistemas de transmissão passa-faixa, uma recepção coerente satisfatória é dificil de ser alcancada. Para alguns destes sistemas, é comum supor que a rotaçãoo de fase introduzida pelo canal é constante durante um bloco de L simbolos e que ela varia de maneira independente de bloco a bloco. Este canal é denominado canal não-coerente de bloco. Investigamos a capacidade de um canal não-coerente de bloco utilizando a modulação M-APSK (do inglês, M-ary Amplitude Phase Shift Keying). Apresentamos a caracterização da distribuição de entrada que atinge a capacidade e obtivemos limitantes superiores e inferiores para a mesma. Adicionalmente, desenvolvemos um algoritmo que simultaneamente fornece a distribuição de entrada e os parametros da modulação M-APSK que maximizam a informação mutua com recepção coerente. A investigação da capacidade mostrou que o aumento de L faz a capacidade não-coerente convergir para a coerente. Alem disso, o uso de codificação diferencial torna a convergência mais rapida. Motivados por este comportamento, apresentamos um esquema de codificação eficiente em faixa. Este esquema é formado pela concatenação serial de um codigo LDPC (do ingles, Low-Density Parity Check ), um entrela¸cador e um codificador diferencial. Para o esquema apresentado, o receptor iterativo é descrito por um grafo-fator. Os desempenhos do esquema com diferentes tamanhos de codigos LDPC são comparados / Abstract: Coherent reception is not possible for many bandpass transmission systems. In some of these systems, it is commonly assumed that the unknown carrier phase rotation is constant over a block of L symbols and it is independent from block to block. This channel is denominated blockwise noncoherent channel. The blockwise noncoherent channel capacity using M-ary Amplitude and Phase Shift Keying (M-APSK) modulation is investigated. The characterization of the input distribution achieving capacity is presented. Upper and lower bounds to this capacity are derived. In addition, an algorithm for simultaneously computing the input distribution and the M-APSK constellation parameters which maximizes the mutual information with coherent reception is developed. The investigation of the capacity showed that as L increases, the noncoherent capacity converges to the coherent one. Besides that, the use of differential encoding makes this convergence faster. Motivated by this fact, a bandwidth efficient coding scheme is presented. This scheme is composed of a serial concatenation of a Low-Density Parity Check (LDPC) code, an interleaver, and a differential encoder. For this scheme, the iterative receiver is described by a factor graph. The scheme performances for different lengths of LDPC codes are compared. / Doutorado / Telecomunicações e Telemática / Doutor em Engenharia Elétrica
32

LDPC kódy / LDPC codes

Hrouza, Ondřej January 2012 (has links)
The aim of this thesis are problematics about LDPC codes. There are described metods to create parity check matrix, where are important structured metods using finite geometry: Euclidean geometry and projectice geometry. Next area in this thesis is decoding LDPC codes. There are presented four metods: Hard-Decision algorithm, Bit-Flipping algorithm, The Sum-Product algorithm and Log Likelihood algorithm, where is mainly focused on iterative decoding methods. Practical output of this work is program LDPC codes created in environment Matlab. The program is divided to two parts -- Practise LDPC codes and Simulation LDPC codes. The result reached by program Simulation LDPC codes is used to create a comparison of creating and decoding methods LDPC codes. For comparison of decoding methods LDPC codes were used BER characteristics and time dependence each method on various parameters LDPC code (number of iteration or size of parity matrix).
33

High Speed Turbo Tcm Ofdm For Uwb And Powerline System

Wang, Yanxia 01 January 2006 (has links)
Turbo Trellis-Coded Modulation (TTCM) is an attractive scheme for higher data rate transmission, since it combines the impressive near Shannon limit error correcting ability of turbo codes with the high spectral efficiency property of TCM codes. We build a punctured parity-concatenated trellis codes in which a TCM code is used as the inner code and a simple parity-check code is used as the outer code. It can be constructed by simple repetition, interleavers, and TCM and functions as standard TTCM but with much lower complexity regarding real world implementation. An iterative bit MAP decoding algorithm is associated with the coding scheme. Orthogonal Frequency Division Multiplexing (OFDM) modulation has been a promising solution for efficiently capturing multipath energy in highly dispersive channels and delivering high data rate transmission. One of UWB proposals in IEEE P802.15 WPAN project is to use multi-band OFDM system and punctured convolutional codes for UWB channels supporting data rate up to 480Mb/s. The HomePlug Networking system using the medium of power line wiring also selects OFDM as the modulation scheme due to its inherent adaptability in the presence of frequency selective channels, its resilience to jammer signals, and its robustness to impulsive noise in power line channel. The main idea behind OFDM is to split the transmitted data sequence into N parallel sequences of symbols and transmit on different frequencies. This structure has the particularity to enable a simple equalization scheme and to resist to multipath propagation channel. However, some carriers can be strongly attenuated. It is then necessary to incorporate a powerful channel encoder, combined with frequency and time interleaving. We examine the possibility of improving the proposed OFDM system over UWB channel and HomePlug powerline channel by using our Turbo TCM with QAM constellation for higher data rate transmission. The study shows that the system can offer much higher spectral efficiency, for example, 1.2 Gbps for OFDM/UWB which is 2.5 times higher than the current standard, and 39 Mbps for OFDM/HomePlug1.0 which is 3 times higher than current standard. We show several essential requirements to achieve high rate such as frequency and time diversifications, multi-level error protection. Results have been confirmed by density evolution. The effect of impulsive noise on TTCM coded OFDM system is also evaluated. A modified iterative bit MAP decoder is provided for channels with impulsive noise with different impulsivity.
34

Applications of Random Graphs to Design and Analysis of LDPC Codes and Sensor Networks

19 August 2005 (has links)
This thesis investigates a graph and information theoretic approach to design and analysis of low-density parity-check (LDPC) codes and wireless networks. In this work, both LDPC codes and wireless networks are considered as random graphs. This work proposes solutions to important theoretic and practical open problems in LDPC coding, and for the first time introduces a framework for analysis of finite wireless networks. LDPC codes are considered to be one of the best classes of error-correcting codes. In this thesis, several problems in this area are studied. First, an improved decoding algorithm for LDPC codes is introduced. Compared to the standard iterative decoding, the proposed decoding algorithm can result in several orders of magnitude lower bit error rates, while having almost the same complexity. Second, this work presents a variety of bounds on the achievable performance of different LDPC coding scenarios. Third, it studies rate-compatible LDPC codes and provides fundamental properties of these codes. It also shows guidelines for optimal design of rate-compatible codes. Finally, it studies non-uniform and unequal error protection using LDPC codes and explores their applications to data storage systems and communication networks. It presents a new error-control scheme for volume holographic memory (VHM) systems and shows that the new method can increase the storage capacity by more than fifty percent compared to previous schemes. This work also investigates the application of random graphs to the design and analysis of wireless ad hoc and sensor networks. It introduces a framework for analysis of finite wireless networks. Such framework was lacking from the literature. Using the framework, different network properties such as capacity, connectivity, coverage, and routing and security algorithms are studied. Finally, connectivity properties of large-scale sensor networks are investigated. It is shown how unreliability of sensors, link failures, and non-uniform distribution of nodes affect the connectivity of sensor networks.
35

Applications of Random Graphs to Design and Analysis of LDPC Codes and Sensor Networks

Pishro-Nik, Hossein 12 1900 (has links)
This thesis investigates a graph and information theoretic approach to design and analysis of low-density parity-check (LDPC) codes and wireless networks. In this work, both LDPC codes and wireless networks are considered as random graphs. This work proposes solutions to important theoretic and practical open problems in LDPC coding, and for the first time introduces a framework for analysis of finite wireless networks. LDPC codes are considered to be one of the best classes of error-correcting codes. In this thesis, several problems in this area are studied. First, an improved decoding algorithm for LDPC codes is introduced. Compared to the standard iterative decoding, the proposed decoding algorithm can result in several orders of magnitude lower bit error rates, while having almost the same complexity. Second, this work presents a variety of bounds on the achievable performance of different LDPC coding scenarios. Third, it studies rate-compatible LDPC codes and provides fundamental properties of these codes. It also shows guidelines for optimal design of rate-compatible codes. Finally, it studies non-uniform and unequal error protection using LDPC codes and explores their applications to data storage systems and communication networks. It presents a new error-control scheme for volume holographic memory (VHM) systems and shows that the new method can increase the storage capacity by more than fifty percent compared to previous schemes. This work also investigates the application of random graphs to the design and analysis of wireless ad hoc and sensor networks. It introduces a framework for analysis of finite wireless networks. Such framework was lacking from the literature. Using the framework, different network properties such as capacity, connectivity, coverage, and routing and security algorithms are studied. Finally, connectivity properties of large-scale sensor networks are investigated. It is shown how unreliability of sensors, link failures, and non-uniform distribution of nodes affect the connectivity of sensor networks.
36

Comparison Of Decoding Algorithms For Low-density Parity-check Codes

Kolayli, Mert 01 September 2006 (has links) (PDF)
Low-density parity-check (LDPC) codes are a subclass of linear block codes. These codes have parity-check matrices in which the ratio of the non-zero elements to all elements is low. This property is exploited in defining low complexity decoding algorithms. Low-density parity-check codes have good distance properties and error correction capability near Shannon limits. In this thesis, the sum-product and the bit-flip decoding algorithms for low-density parity-check codes are implemented on Intel Pentium M 1,86 GHz processor using the software called MATLAB. Simulations for the two decoding algorithms are made over additive white gaussian noise (AWGN) channel changing the code parameters like the information rate, the blocklength of the code and the column weight of the parity-check matrix. Performance comparison of the two decoding algorithms are made according to these simulation results. As expected, the sum-product algorithm, which is based on soft-decision decoding, outperforms the bit-flip algorithm, which depends on hard-decision decoding. Our simulations show that the performance of LDPC codes improves with increasing blocklength and number of iterations for both decoding algorithms. Since the sum-product algorithm has lower error-floor characteristics, increasing the number of iterations is more effective for the sum-product decoder compared to the bit-flip decoder. By having better BER performance for lower information rates, the bit-flip algorithm performs according to the expectations / however, the performance of the sum-product decoder deteriorates for information rates below 0.5 instead of improving. By irregular construction of LDPC codes, a performance improvement is observed especially for low SNR values.
37

Parallelized Architectures For Low Latency Turbo Structures

Gazi, Orhan 01 January 2007 (has links) (PDF)
In this thesis, we present low latency general concatenated code structures suitable for parallel processing. We propose parallel decodable serially concatenated codes (PDSCCs) which is a general structure to construct many variants of serially concatenated codes. Using this most general structure we derive parallel decodable serially concatenated convolutional codes (PDSCCCs). Convolutional product codes which are instances of PDSCCCs are studied in detail. PDSCCCs have much less decoding latency and show almost the same performance compared to classical serially concatenated convolutional codes. Using the same idea, we propose parallel decodable turbo codes (PDTCs) which represent a general structure to construct parallel concatenated codes. PDTCs have much less latency compared to classical turbo codes and they both achieve similar performance. We extend the approach proposed for the construction of parallel decodable concatenated codes to trellis coded modulation, turbo channel equalization, and space time trellis codes and show that low latency systems can be constructed using the same idea. Parallel decoding operation introduces new problems in implementation. One such problem is memory collision which occurs when multiple decoder units attempt accessing the same memory device. We propose novel interleaver structures which prevent the memory collision problem while achieving performance close to other interleavers.
38

Ανάλυση, σχεδιασμός και υλοποίηση κωδίκων διόρθωσης λαθών για τηλεπικοινωνιακές εφαρμογές υψηλών ταχυτήτων

Αγγελόπουλος, Γεώργιος 20 October 2009 (has links)
Σχεδόν όλα τα σύγχρονα τηλεπικοινωνιακά συστήματα, τα οποία προορίζονται για αποστολή δεδομένων σε υψηλούς ρυθμούς, έχουν υιοθετήσει κώδικες διόρθωσης λαθών για την αύξηση της αξιοπιστίας και τη μείωση της απαιτούμενης ισχύος εκπομπής τους. Μια κατηγορία κωδίκων, και μάλιστα με εξαιρετικές επιδόσεις, είναι η οικογένεια των LPDC κωδίκων (Low-Density-Parity-Check codes). Οι κώδικες αυτοί είναι γραμμικοί block κώδικες με απόδοση πολύ κοντά στο όριο του Shannon. Επιπλέον, ο εύκολος παραλληλισμός της διαδικασίας αποκωδικοποίησής τους, τους καθιστά κατάλληλους για υλοποίηση σε υλικό. Στην παρούσα διπλωματική μελετούμε τα ιδιαίτερα χαρακτηριστικά και τις παραμέτρους των κωδίκων αυτών, ώστε να κατανοήσουμε την εκπληκτική διορθωτική ικανότητά τους. Στη συνέχεια, επιλέγουμε μια ειδική κατηγορία κωδίκων LDPC, της οποίας οι πίνακες ελέγχου ισοτιμίας έχουν δημιουργηθεί ώστε να διευκολύνουν την υλοποίησή τους, και προχωρούμε στο σχεδιασμό αυτής σε υλικό. Πιο συγκεκριμένα, υλοποιούμε σε VHDL έναν αποκωδικοποιητή σύμφωνα με τον rate ½ και block_lenght 576 bits πίνακα του προτύπου WiMax 802.16e, με στόχο κυρίως την επίτευξη πολύ υψηλού throughput. Στο χρονοπρογραμματισμό της μετάδοσης των μηνυμάτων μεταξύ των κόμβων του κυκλώματος χρησιμοποιούμε το two-phase scheduling και προτείνουμε δύο τροποποιήσεις αυτού για την επιτάχυνση της διαδικασίας αποκωδικοποίησης, οι οποίες καταλήγουν σε 24 και 50% βελτίωση του απαιτούμενου χρόνου μιας επανάληψης με μηδενική και σχετικά μικρή αύξηση της επιφάνειας ολοκλήρωσης αντίστοιχα. Ο όλος σχεδιασμός είναι πλήρως συνθέσιμος και η σωστή λειτουργία αυτού έχει επιβεβαιωθεί σε επίπεδο λογικής εξομοίωσης. Κατά τη διάρκεια σχεδιασμού, χρησιμοποιήθηκαν εργαλεία της Xilinx και MentorGraphics. / Αlmost all the modern telecommunication systems, which are designed for high data rate transmissions, have adopted error correction codes for improving the reliability and the required power of transmission. One special group of these codes, with extremely good performance, is the LDPC codes (Low-Density-Parity-Check codes). These codes are linear block codes with performance near to the theoretical Shannon limit. Furthermore, the inherent parallelism of the decoding procedure makes them suitable for implementation on hardware. In this thesis, we study the special characteristics of these codes in order to understand their astonishing correcting capability. Then, we choose a special category of these codes, whose parity check matrix are special designed to facilitate their implementation on hardware, and we design a high-throughput decoder. More specifically, we implement in VHDL an LDPC decoder according to the rate ½ and block_length 576 bits code of WiMax IEEE802.16e standard, with main purpose to achieve very high throughput. We use the two-phase scheduling at the message passing and we propose 2 modifications for reducing the required decoding time, which result in 25 and 50% improving of the required decoding time of one iteration with zero and little increasing in the decoder’s area respectively. Our design has been successfully simulated and synthesized. During the design process, we used Xiinx and MentorGraphics’s tools.
39

Adaptive Concatenated Coding for Wireless Real-Time Communications

Uhlemann, Elisabeth January 2004 (has links)
The objective of this thesis is to improve the performance of real-time communication overa wireless channel, by means of specifically tailored channel coding. The deadlinedependent coding (DDC) communication protocol presented here lets the timeliness and thereliability of the delivered information constitute quality of service (QoS) parametersrequested by the application. The values of these QoS parameters are transformed intoactions taken by the link layer protocol in terms of adaptive coding strategies.Incremental redundancy hybrid automatic repeat request (IR-HARQ) schemes usingrate compatible punctured codes are appealing since no repetition of previously transmittedbits is made. Typically, IR-HARQ schemes treat the packet lengths as fixed and maximizethe throughput by optimizing the puncturing pattern, i.e. the order in which the coded bitsare transmitted. In contrast, we define an IR strategy as the maximum number of allowedtransmissions and the number of code bits to include in each transmission. An approach isthen suggested to find the optimal IR strategy that maximizes the average code rate, i.e., theoptimal partitioning of n-kparity bits over at most M transmissions, assuming a givenpuncturing pattern. Concatenated coding used in IR-HARQ schemes provides a new arrayof possibilities for adaptability in terms of decoding complexity and communication timeversus reliability. Hence, critical reliability and timing constraints can be readily evaluatedas a function of available system resources. This in turn enables quantifiable QoS and thusnegotiable QoS. Multiple concatenated single parity check codes are chosen as examplecodes due to their very low decoding complexity. Specific puncturing patterns for thesecomponent codes are obtained using union bounds based on uniform interleavers. Thepuncturing pattern that has the best performance in terms of frame error rate (FER) at a lowsignal-to-noise ratio (SNR) is chosen. Further, using extrinsic information transfer (EXIT)analysis, rate compatible puncturing ratios for the constituent component code are found.The puncturing ratios are chosen to minimize the SNR required for convergence.The applications targeted in this thesis are not necessarily replacement of cables inexisting wired systems. Instead the motivation lies in the new services that wireless real-time communication enables. Hence, communication within and between cooperatingembedded systems is typically the focus. The resulting IR-HARQ-DDC protocol presentedhere is an efficient and fault tolerant link layer protocol foundation using adaptiveconcatenated coding intended specifically for wireless real-time communications. / Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie, 2198, Technical report. D, 29,
40

Iterative joint detection and decoding of LDPC-Coded V-BLAST systems

Tsai, Meng-Ying (Brady) 10 July 2008 (has links)
Soft iterative detection and decoding techniques have been shown to be able to achieve near-capacity performance in multiple-antenna systems. To obtain the optimal soft information by marginalization over the entire observation space is intractable; and the current literature is unable to guide us towards the best way to obtain the suboptimal soft information. In this thesis, several existing soft-input soft-output (SISO) detectors, including minimum mean-square error-successive interference cancellation (MMSE-SIC), list sphere decoding (LSD), and Fincke-Pohst maximum-a-posteriori (FPMAP), are examined. Prior research has demonstrated that LSD and FPMAP outperform soft-equalization methods (i.e., MMSE-SIC); however, it is unclear which of the two scheme is superior in terms of performance-complexity trade-off. A comparison is conducted to resolve the matter. In addition, an improved scheme is proposed to modify LSD and FPMAP, providing error performance improvement and a reduction in computational complexity simultaneously. Although list-type detectors such as LSD and FPMAP provide outstanding error performance, issues such as the optimal initial sphere radius, optimal radius update strategy, and their highly variable computational complexity are still unresolved. A new detection scheme is proposed to address the above issues with fixed detection complexity, making the scheme suitable for practical implementation. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-07-08 19:29:17.66

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