Thesis (M.S.)--Naval Postgraduate School, 2002. / Thesis advisor(s): Murali Tummala, Robert Ives. Includes bibliographical references (p. 95-97). Also available online.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 63-65). Also available in electronic version. Access restricted to campus users.

Thesis (M.S. in Applied Math and M.S. in Systems Engineering)--Naval Postgraduate School, March 2003. / Thesis advisor(s): Roberto Cristi, Ron Pieper, Craig Rasmussen. Includes bibliographical references (p. 119-121). Also available online.

The report detailing the Hardware Accelerator for the JPEG encoder is organized into three sections. First, it will review the processes of the Joint Photographic Experts Group (JPEG) encoding and decoding standard. Second, it will review three different implementations of the discrete cosine transform in hardware. This is a very computationally intensive element of the JPEG encoding process and the analysis of these designs covers the benefits and costs of the various approaches for the Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations. Finally, it will discuss this specific hardware accelerator design for a color state transformation for the standard JPEG encoder. An eight by eight matrix of Red, Green, Blue (RGB) values is passed into the FPGA as well as calculated in software. The Y Cr Cb results from that of the hardware accelerator implementation are compared with the software implementation for computational accuracy and the differences in computation time are sampled for a comparison. There is a clear 38% improvement in speed from the hardware accelerator. / text

For any practical implementation of chip design, there needs to be a hardware platform available for the purpose of prototyping and implementation of FPGA-based programs, whether they are written in VHDL or Verilog. Communication between the platform and a computer is a useful feature of many hardware solutions as it allows for the capability of regular data transmission between the two devices. Furthermore, the ability to communicate between the platform and a computer at high-speeds requires a specially constructed interface, one that can be modified by the designer at their choosing. There are a number of commercial packages which provide a hardware platform to perform this task, however there are drawbacks to many of the available options. Some may require special hardware to connect to a computer using proprietary connectors or boards, which increases the cost and reduces the flexibility of any solution. Other options may have limited access to the internal structure of the interface, limiting the ability of the developer to modify the interface to suit their needs. There may be an extra cost to provide the code to the interface, separate from the board, which can also tax design budgets. This dissertation provides a solution in the form of a Gigabit Ethernet connection with a custom IP/network layer written in VHDL to facilitate the connection. With an increasing number of IP-enabled devices available such as IPTV and set top boxes, the ability to link hardware using Ethernet is very useful and so the development of a lean and capable network layer was considered a suitable focus for the project. The overall goal has been to provide an interface which is cheap, open, robust and efficient, retaining the flexibility a developer might require to modify the code to their needs. After covering some basic background information about the project, the dissertation looks at the requirements of the board and interface, as well as the alternative interface solutions which were looked at before deciding on Gigabit Ethernet. The protocols used in Ethernet are then covered, with both an explanation of the structure of each and their relevance to the implementation. The Finite State Machines which control operation of the interface are covered in depth, with an explanation of their inter-connectivity to each other and how they fit in the data-flow between the computer and the board. Error correction and reliability is discussed, as well as any remaining components critical to the operation of the interface. Pipelining, the method of design which provides the speed required for Gigabit Ethernet, is covered along with the extra speed optimisation techniques used in the design such as RAM swinging buffers. Testing and synthesis are covered which ensure the design is as robust as possible, both in simulations and in real-world applications. The final design was implemented on a Xilinx Spartan 3 FPGA (XC3S5000-5FG900C) and capable of a maximum speed of 128.287 MHz, which is more than enough to satisfy the requirements of Gigabit Ethernet under a variety of network conditions. The interface code occupies 1,166 slices of logic on the FPGA (3% of the total amount of logic available), making it sufficiently compact to run large projects on the same chip. The core was tested on physical hardware and performed correctly at real line Gigabit speeds. Configuration of the computer along with the method of connecting to the board and transferring data is mentioned, with explanation of the code run on the computer to make this possible. Finally, the dissertation provides an example application through the use of JPEG2000 image compression/decompression.

Thesis (M.S.)--University of Delaware, 2007. / Principal faculty advisor: Charles G. Boncelet, Dept. of Computer & Information Sciences. Includes bibliographical references.

Thèse (M.Sc.)--Université Laval, 2007. / Titre de l'écran-titre (visionné le 9 mai 2008). Bibliogr.

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Approved for public release; distribution is unlimited / Perceptual watermarking is a promising technique towards the goal of producing invisible watermarks. It involves the integration of formal perceptual models in the watermarking process, with the purpose of determining those portions of an image that can better tolerate the distortion imposed by the embedding and ensuring that the watermarking will inflict the least possible degradation on the original image . In a previous study the Discrete Cosine Transform was used, and the watermark embedding was done in a non -uniform manner with criteria based on both the host image and the watermark. The decoder model employed made use of apriori access to unmarked and marked images as well as to the watermark. A fair level of success was achieved in this effort. In our research we refine this scheme by integrating a perceptual model and by proposing a modification to the decoder model that makes possible the successful recovery of the watermark without apriori access to it. The proposed perceptual scheme improves the watermark's transparency while at the same time maintains sufficient robustness to quantization and cropping. The proposed semi-blind variation offers adequate transparency and robustness to quantization, but its performance against cropping is considerably degraded. / Lieutenant, Hellenic Navy

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.