Technologijos greitai keičiasi, kasdien atsiranda mokslo ir technikos naujovių, kurios daugiau ar mažiau įtakoja mūsų kasdieninį gyvenimą. Skaitmeninės technologijos atnešė daug naujovių ir galima numanyti, kad jų bus dar daugiau. Skaitmenizavimo procesas tęsiasi ir apima dar likusias analogines erdves. Ypatingai šis procesas svarbus komunikacijų srityje Darbe stengtasi išsiaiškinti ir ištirti DVI veikimo principus bei suprojektuoti šios sąsajos modifikaciją, besiremiančia suspaustų vaizdų perdavimo technologija. Darbe susiduriama su vaizdo duomenų formavimo, perdavimo ir atvaizdavimo mechanizmais. Tuo pat panagrinėjant įvairius nestandartinius šio mechanizmo atvejus, kurie galbūt dabar nėra komerciškai efektyvūs, bet galėtų rasti labai specifinį panaudojimą ir būtent jame taptų nepakeičiamai naudingi. Nuspręsta imtis skaitmeninės DVI sąsajos (angl. digital visual interface). Atliekamų funkcijų atskyrimui naudojama blokinė dekompozicija, apžvelgiamos aparatūrinės ir programinės užsibrėžtos sistemos kūrimo priemonės. Kadangi DVI sąsaja jungiamas kompiuteris ir skaitmeninis monitorius paprastai yra vienas nuo kito netoli, nuspręsta pabandyti kaip pavyktų šį atstumą pailginti neapibrėžtai daug, kitaip tariant vaizdą perduoti naudojant įprastą ethernet tipo laidą, duomenų formatą pakeičiant į paketinį - IP (interneto protokolą) bei su kokiomis pagrindinėmis problemomis susiduriama tai darant. Darbe nagrinėjama ir iškeltos funkcijos ar jos dalies perkėlimo į lustą galimybė. / The study tries to clear out how does the digital video data transfer system works. The scope is about DVI interface and similar systems. Also the design of compressed video data transfer mechanisms. The things touched are very different and not even very popular in deed but in some cases they can become a very useful decision for some non standard applications. The study mainly touches digital visual interface – DVI. In case that DVI interface connected computer and monitor must be really near each other it was decided to enlong this distance. In other words – to transfer video data through Ethernet cable and changing and compressing DVI video data format into packets. All study stands for it and tries to clarify the main problems and difficulties doing that.

Šiame technologijų amžiuje vis daugiau technologijų sąveikauja su aplinka. Tai įvairūs prietaisai, sistemos, robotai, kurie geba apdoroti vaizdinę informaciją ir/arba ją interpretuoti. Kadangi vaizdinė informacija užima labai daug kietojo disko vietos, palyginus su kitokios rūšies informacija, iškyla jos saugojimo bei parsiuntimo problemos. Šioms problemoms spręsti pasitelkiamas duomenų glaudinimas (data compression). Šie sprendimai gali būti įgyvendinti programiškai (software) ir aparatūriškai (hardware). Aparatūriniai sprendimai pasižymi dideliu greičiu taip pat panaudojimo galimybėmis. Kadangi ateityje technologijos vis labiau sąveikaus su aplinka, įrenginiai, sugebantys greitai, tiksliai ir kuo mažesnėmis kietojo disko sąnaudomis apdoroti vaizdus, taps ypač reikšmingi. Tokius įrenginius patogu projektuoti ir tirti naudojantis aparatūros aprašymo kalbomis (angl. Hardware Description Language). Taip pat svarbus šių įrenginių aspektas – vis didėjantis jų sudėtingumas. Pakartotinio naudojimo (reuse) metodologija – naudojimas sukurtų ir verifikuotų komponentų – dabar yra kertinis lustų bei SOC (System On Chip) kūrimo akmuo, kadangi tai yra metodologija, kuri leidžia sudėtingus lustus projektuoti prieinama kaina, geresnės kokybės taip pat taupo žmogiškuosius išteklius ir laiką. / In this age of technological advances more and more technologies interact with environment. It is various devices, systems, robots which are capable to process and/or interpret visual information. Visual information is very space consuming information in comparison with other types of information, so problems like storing, downloading emerges and data compression is trying to resolve these problems. These data compression solutions may be implemented using software or hardware. Hardware solutions characterized with their high speed. In future more and more technologies will be capable to interact with environment, so tools capable of fast, precise and good compression render of images will become very important. These tools may be designed and studied using hardware description languages. Furthermore, visual information processing tools becoming very complex. Reuse methodology enables easier, faster and cheaper design of such tools.

Made available in DSpace on 2014-06-12T17:40:49Z (GMT). No. of bitstreams: 2 arquivo7042_1.pdf: 3910655 bytes, checksum: 9a5e52d2535f94f8e232ee5d957d91ee (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2005 / Recentemente, foram desenvolvidos algoritmos iterativos de compressão destinados à transmissão de imagens estáticas via rede tais como: JPEG progressivo, JPEG2000 progressivo, PNG entrelaçado e GIF entrelaçado. Esses algoritmos decompõem a imagem e a transmitem de forma não seqüencial. O propósito desta dissertação consiste em efetuar um estudo comparativo desses algoritmos. A metodologia adotada consiste em fazer uma análise das imagens parciais obtidas para cada formato. Em cada etapa, faz-se uma inspeção visual da imagem e mede-se o PSNR (Peak Signal-to-Noise Ratio) em relação à imagem final, um fator objetivo de qualidade de imagens. Parâmetros como tamanho do arquivo parcial, natureza da imagem e inspeção visual também são alvo de estudo. Através de uma análise detalhada das imagens parciais obtidas somos capazes de definir então qual algoritmo é mais apropriado em cada etapa da transmissão de acordo com a natureza da imagem analisada

JPEG2000 is a recently standardized image compression system that provides substantial improvements over the existing JPEG compression scheme. This improvement in performance comes with an associated cost in increased implementation complexity, such that a purely software implementation is inefficient. This work identifies the arithmetic coder as a bottleneck in efficient hardware implementations, and explores various design options to improve arithmetic coder speed and size. The designs produced improve the critical path of the existing arithmetic coder designs, and then extend the coder throughput to 2 or more symbols per clock cycle. Subsequent work examines more system level implementation issues. This work examines the communication between hardware blocks and utilizes certain modes of operation to add flexibility to buffering solutions. It becomes possible to significantly reduce the amount of intermediate buffering between blocks, whilst maintaining a loose synchronization. Full hardware implementations of the standard are necessarily limited in the amount of features that they can offer, in order to constrain complexity and cost. To circumvent this, a hardware / software codesign is produced using the Altera NIOS II softcore processor. By keeping the majority of the standard implemented in software and using hardware to accelerate those time consuming functions, generality of implementation can be retained, whilst implementation speed is improved. In addition to this, there is the opportunity to explore parallelism, by providing multiple identical hardware blocks to code multiple data units simultaneously.

The Key algorithms of JPEG2000, the new image compression standard, have high computational complexity and thus present challenges for efficient implementation. This has led to research on the hardware optimization of JPEG2000 for its efficient realization. Luckily, in the last century the growth in Microelectronics allows us to realize dedicated ASIC solutions as well as hardware/software FPGA based solutions for complex algorithms such as JPEG2000. But an efficient implementation within hard constraints of area and throughput, demands investigations of key dependencies within the JPEG2000 system. This work presents algorithms and VLSI architectures to realize a high performance JPEG2000 compression system. The embedded block coding algorithm which lies at the heart of a JPEG2000 compression system is a main contributor to enhanced JPEG2000 complexity. This work first concentrates on algorithms to realize low-cost high throughput Block Coder (BC) system. For this purpose concurrent symbol processing capable Bit Plane Coder architecture is presented. Further optimal 2 sub-bank memory and an efficient buffer architectures are designed to keep the hardware cost low. The proposed overall BC system presents the highest Figure Of Merit (FOM) in terms of throughput versus hardware cost in comparison to existing BC solutions. Further, this work also investigates the challenges involved in the efficient integration of the BC with the overall JPEG2000 system. A novel low-cost distortion estimation approach with near-optimal performance is proposed which is necessary for accurate rate-control performance of JPEG2000. Additionally low bandwidth data storage and transfer techniques are proposed for efficient transfer of subband samples to the BC. Simulation results show that the proposed techniques have approximately 4 times less bandwidth than existing architectures. In addition, an efficient high throughput block decoder architecture based on the proposed selective sample-skipping algorithm is presented. The proposed architectures are designed and analyzed on both ASIC and FPGA platforms. Thus, the proposed algorithms, architectures and efficient BC integration strategies are useful for realizing a dedicated ASIC JPEG2000 system as well as a hardware/software FPGA based JPEG2000 solution. Overall this work presents algorithms and architectures to realize a high performance JPEG2000 system without imposing any restrictions in terms of coding modes or block size for the BC system.

Digital watermarking of multimedia content has been proposed as a method for different applications such as copyright protection, content authentication, transaction tracking and data hiding. In this thesis, we propose a lossless watermarking approach based on Discrete Cosine Transform (DCT) for a new application of watermarking. A depth map obtained from a stereoscopic image pair is embedded into one of the two images using a reversible watermarking algorithm. Different from existing approaches which hide depth map in spatial domain, the depth information is hidden in the quantized DCT domain of the stereo image in our method. This modification makes the watermarking algorithm compatible with JPEG and MPEG-2 compression. After the investigation of the quantized DCT coefficients distribution of the compressed image and video, The bit-shift operation is utilized to embed the depth map into its associated 2D image reversibly for the purpose of achieving high compression efficiency of the watermarked image and/or video and high visual quality of stereo image and/or video after the depth map is extracted. We implement the proposed method to analyze its performance. The experimental results show that a very high payload of watermark (e.g. depth map) can be embedded into the JPEG compressed image and MPEG-2 video. The compression efficiency is only slightly reduced after the watermark embedding and the quality of the original image or video can be restored completely at the decoder side.

This thesis presents an architecture and an FPGA implementation of the two dimensional discrete wavelet transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the iii DWT module and the amount of locally stored image data, is a function of the image and tile size. For an n1 &times / n2 size image processed using (n1/k1) &times / (n2/k2) sized tiles the latency is equal to the time elapsed to accumulate a (1/k1) portion of one image. In addition, a (2/k1) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG 2000 compression system designed as a payload for a low earth orbit (LEO) micro-satellite to be launched in September 2003. The architecture can achieve a throughput of up to 160Mbit/s. The latency introduced is 0.105 sec (6.25% of total transmission time) for tile sizes of 256&times / 256. The local storage size required for the tiling operation is 2 MB. The internal storage requirement is 1536 pixels. Equivalent gate count for the design is 292,447.

Digital watermarking of multimedia content has been proposed as a method for different applications such as copyright protection, content authentication, transaction tracking and data hiding. In this thesis, we propose a lossless watermarking approach based on Discrete Cosine Transform (DCT) for a new application of watermarking. A depth map obtained from a stereoscopic image pair is embedded into one of the two images using a reversible watermarking algorithm. Different from existing approaches which hide depth map in spatial domain, the depth information is hidden in the quantized DCT domain of the stereo image in our method. This modification makes the watermarking algorithm compatible with JPEG and MPEG-2 compression. After the investigation of the quantized DCT coefficients distribution of the compressed image and video, The bit-shift operation is utilized to embed the depth map into its associated 2D image reversibly for the purpose of achieving high compression efficiency of the watermarked image and/or video and high visual quality of stereo image and/or video after the depth map is extracted. We implement the proposed method to analyze its performance. The experimental results show that a very high payload of watermark (e.g. depth map) can be embedded into the JPEG compressed image and MPEG-2 video. The compression efficiency is only slightly reduced after the watermark embedding and the quality of the original image or video can be restored completely at the decoder side.

Digital watermarking of multimedia content has been proposed as a method for different applications such as copyright protection, content authentication, transaction tracking and data hiding. In this thesis, we propose a lossless watermarking approach based on Discrete Cosine Transform (DCT) for a new application of watermarking. A depth map obtained from a stereoscopic image pair is embedded into one of the two images using a reversible watermarking algorithm. Different from existing approaches which hide depth map in spatial domain, the depth information is hidden in the quantized DCT domain of the stereo image in our method. This modification makes the watermarking algorithm compatible with JPEG and MPEG-2 compression. After the investigation of the quantized DCT coefficients distribution of the compressed image and video, The bit-shift operation is utilized to embed the depth map into its associated 2D image reversibly for the purpose of achieving high compression efficiency of the watermarked image and/or video and high visual quality of stereo image and/or video after the depth map is extracted. We implement the proposed method to analyze its performance. The experimental results show that a very high payload of watermark (e.g. depth map) can be embedded into the JPEG compressed image and MPEG-2 video. The compression efficiency is only slightly reduced after the watermark embedding and the quality of the original image or video can be restored completely at the decoder side.

Αντικείμενο της εργασίας είναι η δημιουργία ενός ολοκληρωμένου συστήματος με DSP για λήψη, κωδικοποίηση σύμφωνα με το πρότυπο JPEG και αποστολή εικόνας με τη βοήθεια του πρωτοκόλλου TCP/IP. Η ανάπτυξη της εφαρμογής έγινε σε γλώσσα προγραμματισμού c, ενώ ο έλεγχος του συστήματος γίνεται μέσω ενός γραφικού περιβάλλοντος αλληλεπίδρασης με το χρήστη. Στο πρώτο κεφάλαιο περιγράφεται η αναπτυξιακή πλατφόρμα DSK C6416T. Γίνεται αναφορά στην αρχιτεκτονική του επεξεργαστή ψηφιακού σήματος TMSC3206416T της εταιρείας Texas Instruments καθώς και στις υπόλοιπες περιφερειακές συσκευές. Στο δεύτερο κεφάλαιο περιγράφεται η αρχιτεκτονική της θυγατρικής κάρτας DSKeye Gigabit της εταιρείας Bitec, που συνδέεται στο DSK. Η κάρτα αυτή διαχειρίζεται τα δεδομένα για την αποστολή τους μέσω TCP/IP, καθώς και την έγχρωμη κάμερα OV5610 της εταιρείας Omnivision, η οποία είναι απαραίτητη για τη λήψη των εικόνων. Περιγράφεται επίσης ο τρόπος διασύνδεσης όλων των συσκευών από άποψη υλικού, ενώ στη συνέχεια περιγράφεται και η διασύνδεση λογισμικού. Στο τρίτο κεφάλαιο γίνεται αναλυτική περιγραφή του προτύπου JPEG, ιδιαίτερα του τμήματος που αναφέρεται στο Baseline DCT. Ακολουθεί παράδειγμα με το οποίο γίνεται κατανοητή η διαδικασία κωδικοποίησης σύμφωνα με το JPEG πρότυπο. Στο τέταρτο κεφάλαιο περιγράφεται η υλοποίηση του συστήματος, το διάγραμμα ροής του βασικού προγράμματος ενώ παρουσιάζονται τα αποτελέσματα με τη βοήθεια του γραφικού περιβάλλοντος. Τέλος στο παράρτημα αναφέρονται τα είδη EDMA μεταφορών και τρόποι προγραμματισμού. / This master thesis main purpose is to create a complete system using a DSP, for capturing images, encoding them according to the ISO/IEC 10918-1 specification widely known as JPEG and sending them to a remote client using the TCP/IP protocol. The source code was developed using the c programming language and a GUI was built in order to act as the remote client and also to control the capturing procedure. In the first chapter we review the C6416T DSP starter kit module, which incorporates the Texas Instruments 1GHz TMS320C6416T processor. In the next chapter we analyse the DSKeye gigabit daughtercard made by Bitec. This board features a 5.2 Megapixel colour camera used for capturing the desired images in Bayern format and also a gigabit Ethernet interface, allowing us to establish the TCP/IP communication. The following chapter explains the theoretical aspects of a baseline DCT JPEG encoder, laying emphasis on the details of the encoding procedure. Finally we present the flow charts and we summarise our results. The current project is a follow up to Bitec’s “webview” example, which uses the above hardware in order to capture and send a true colour bitmap image to a web browser. We used the DSKeye API with slight modifications in order to overcome memory restrictions imposed by image resolution and overall code size. The TCP stack was accessed using the BSD socket API. The encoder was ported to the DSP from the free JPEG c code available from the Independent JPEG Group. It was developed and tested using Microsoft’s Visual Studio 2005 Express Edition as well as TI’s Code Composer Studio v3.1. Finally the GUI was created using Labview 8.0.