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International Telemetering Conference Proceedings / October 25-28, 1993 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Various forms of 'lossy' and 'lossless' encoding have been implemented or proposed to allow compression of still and motion picture images, with varying degrees of success which in turn depend on how success is defined. Proponents of various systems claim 'compression ratios' which by their nature defy comparison of one system with another and suggest there actually may be something like a free lunch. This paper compares various compression methods as well as the implications involved in using them and what happens when different systems encounter the problems associated with the uses of the restored picture.

Esta dissertação apresenta o desenvolvimento de arquiteturas para a compressão JPEG, onde são apresentadas arquiteturas de um compressor JPEG para imagens em tons de cinza, de um compressor JPEG para imagens coloridas e de um conversor de espaço de cores de RGB para YCbCr. As arquiteturas desenvolvidas são detalhadamente apresentadas, tendo sido completamente descritas em VHDL, com sua síntese direcionada para FPGAs da família Flex10KE da Altera. A arquitetura integrada do compressor JPEG para imagens em tons de cinza possui uma latência mínima de 237 ciclos de clock e processa uma imagem de 640x480 pixels em 18,5ms, permitindo uma taxa de processamento de 54 imagens por segundo. As estimativas realizadas em torno da taxa de compressão obtida indicam que ela seria de aproximadamente 6,2 vezes ou de 84 %. A arquitetura integrada do compressor JPEG para imagens coloridas foi gerada a partir de adaptações na arquitetura do compressor para imagens em tons de cinza. Esta arquitetura também possui a latência mínima de 237 ciclos de clock, sendo capaz de processar uma imagem coloria de 640 x 480 pixels em 54,4ms, permitindo uma taxa de processamento de 18,4 imagens por segundo. A taxa de compressão obtida, segundo estimativas, seria de aproximadamente 14,4 vezes ou de 93 %. A arquitetura para o conversor de espaço de cores de RBG para YCbCr possui uma latência de 6 ciclos de clock e é capaz de processar uma imagem colorida de 640x480 pixels em 84,6ms, o que permite uma taxa de processamento de 11,8 imagens por segundo. Esta arquitetura não chegou a ser integrada com a arquitetura do compressor de imagens coloridas, mas algumas sugestões e estimativas foram realizadas nesta direção. / This dissertation presents the design of architectures for JPEG image compression. Architectures for a gray scale images JPEG compressor that were developed are herein presented. This work also addresses a color images JPEG compressor and a color space converter. The designed architectures are described in detail and they were completely described in VHDL, with synthesis directed for Altera Flex10KE family of FPGAs. The integrated architecture for gray scale images JPEG compressor has a minimum latency of 237 clock cycles and it processes an image of 640x480 pixels in 18,5ms, allowing a processing rate of 54 images per second. The compression rate, according to estimates, would be of 6,2 times or 84%, in percentage of bits compression. The integrated architecture for color images JPEG compression was generated starting from incremental changes in the architecture of gray scale images compressor. This architecture also has the minimum latency of 237 clock cycles and it can process a color image of 640 x 480 pixels in 54,4ms, allowing a processing rate of 18,4 images per second. The compression rate, according to estimates, would be of 14,4 times or 93%, in percentage of bits compression. The architecture for space color conversor from RBG to YCbCr has a latency of 6 clock cycles and it is able to process a color image of 640 x 480 pixels in 84,6ms, allowing a processing rate of 11,8 images per second. This architecture was finally not integrated with the color images compressor architecture, but some suggestions, alternatives and estimates were made in this direction.

Esta dissertação apresenta o desenvolvimento de arquiteturas para a compressão JPEG, onde são apresentadas arquiteturas de um compressor JPEG para imagens em tons de cinza, de um compressor JPEG para imagens coloridas e de um conversor de espaço de cores de RGB para YCbCr. As arquiteturas desenvolvidas são detalhadamente apresentadas, tendo sido completamente descritas em VHDL, com sua síntese direcionada para FPGAs da família Flex10KE da Altera. A arquitetura integrada do compressor JPEG para imagens em tons de cinza possui uma latência mínima de 237 ciclos de clock e processa uma imagem de 640x480 pixels em 18,5ms, permitindo uma taxa de processamento de 54 imagens por segundo. As estimativas realizadas em torno da taxa de compressão obtida indicam que ela seria de aproximadamente 6,2 vezes ou de 84 %. A arquitetura integrada do compressor JPEG para imagens coloridas foi gerada a partir de adaptações na arquitetura do compressor para imagens em tons de cinza. Esta arquitetura também possui a latência mínima de 237 ciclos de clock, sendo capaz de processar uma imagem coloria de 640 x 480 pixels em 54,4ms, permitindo uma taxa de processamento de 18,4 imagens por segundo. A taxa de compressão obtida, segundo estimativas, seria de aproximadamente 14,4 vezes ou de 93 %. A arquitetura para o conversor de espaço de cores de RBG para YCbCr possui uma latência de 6 ciclos de clock e é capaz de processar uma imagem colorida de 640x480 pixels em 84,6ms, o que permite uma taxa de processamento de 11,8 imagens por segundo. Esta arquitetura não chegou a ser integrada com a arquitetura do compressor de imagens coloridas, mas algumas sugestões e estimativas foram realizadas nesta direção. / This dissertation presents the design of architectures for JPEG image compression. Architectures for a gray scale images JPEG compressor that were developed are herein presented. This work also addresses a color images JPEG compressor and a color space converter. The designed architectures are described in detail and they were completely described in VHDL, with synthesis directed for Altera Flex10KE family of FPGAs. The integrated architecture for gray scale images JPEG compressor has a minimum latency of 237 clock cycles and it processes an image of 640x480 pixels in 18,5ms, allowing a processing rate of 54 images per second. The compression rate, according to estimates, would be of 6,2 times or 84%, in percentage of bits compression. The integrated architecture for color images JPEG compression was generated starting from incremental changes in the architecture of gray scale images compressor. This architecture also has the minimum latency of 237 clock cycles and it can process a color image of 640 x 480 pixels in 54,4ms, allowing a processing rate of 18,4 images per second. The compression rate, according to estimates, would be of 14,4 times or 93%, in percentage of bits compression. The architecture for space color conversor from RBG to YCbCr has a latency of 6 clock cycles and it is able to process a color image of 640 x 480 pixels in 84,6ms, allowing a processing rate of 11,8 images per second. This architecture was finally not integrated with the color images compressor architecture, but some suggestions, alternatives and estimates were made in this direction.

Esta dissertação apresenta o desenvolvimento de arquiteturas para a compressão JPEG, onde são apresentadas arquiteturas de um compressor JPEG para imagens em tons de cinza, de um compressor JPEG para imagens coloridas e de um conversor de espaço de cores de RGB para YCbCr. As arquiteturas desenvolvidas são detalhadamente apresentadas, tendo sido completamente descritas em VHDL, com sua síntese direcionada para FPGAs da família Flex10KE da Altera. A arquitetura integrada do compressor JPEG para imagens em tons de cinza possui uma latência mínima de 237 ciclos de clock e processa uma imagem de 640x480 pixels em 18,5ms, permitindo uma taxa de processamento de 54 imagens por segundo. As estimativas realizadas em torno da taxa de compressão obtida indicam que ela seria de aproximadamente 6,2 vezes ou de 84 %. A arquitetura integrada do compressor JPEG para imagens coloridas foi gerada a partir de adaptações na arquitetura do compressor para imagens em tons de cinza. Esta arquitetura também possui a latência mínima de 237 ciclos de clock, sendo capaz de processar uma imagem coloria de 640 x 480 pixels em 54,4ms, permitindo uma taxa de processamento de 18,4 imagens por segundo. A taxa de compressão obtida, segundo estimativas, seria de aproximadamente 14,4 vezes ou de 93 %. A arquitetura para o conversor de espaço de cores de RBG para YCbCr possui uma latência de 6 ciclos de clock e é capaz de processar uma imagem colorida de 640x480 pixels em 84,6ms, o que permite uma taxa de processamento de 11,8 imagens por segundo. Esta arquitetura não chegou a ser integrada com a arquitetura do compressor de imagens coloridas, mas algumas sugestões e estimativas foram realizadas nesta direção. / This dissertation presents the design of architectures for JPEG image compression. Architectures for a gray scale images JPEG compressor that were developed are herein presented. This work also addresses a color images JPEG compressor and a color space converter. The designed architectures are described in detail and they were completely described in VHDL, with synthesis directed for Altera Flex10KE family of FPGAs. The integrated architecture for gray scale images JPEG compressor has a minimum latency of 237 clock cycles and it processes an image of 640x480 pixels in 18,5ms, allowing a processing rate of 54 images per second. The compression rate, according to estimates, would be of 6,2 times or 84%, in percentage of bits compression. The integrated architecture for color images JPEG compression was generated starting from incremental changes in the architecture of gray scale images compressor. This architecture also has the minimum latency of 237 clock cycles and it can process a color image of 640 x 480 pixels in 54,4ms, allowing a processing rate of 18,4 images per second. The compression rate, according to estimates, would be of 14,4 times or 93%, in percentage of bits compression. The architecture for space color conversor from RBG to YCbCr has a latency of 6 clock cycles and it is able to process a color image of 640 x 480 pixels in 84,6ms, allowing a processing rate of 11,8 images per second. This architecture was finally not integrated with the color images compressor architecture, but some suggestions, alternatives and estimates were made in this direction.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / Compressed video is necessary for a variety of telemetry requirements. A large number of competing video compression algorithms exist. This paper compares the ability of these algorithms to meet criteria which are of interest for telemetry applications. Included are: quality, compression, noise susceptibility, motion performance and latency. The algorithms are divided into those which employ inter-frame compression and those which employ intra-frame compression. A video tape presentation will also be presented to illustrate the performance of the video compression algorithms.

ITC/USA 2015 Conference Proceedings / The Fifty-First Annual International Telemetering Conference and Technical Exhibition / October 26-29, 2015 / Bally's Hotel & Convention Center, Las Vegas, NV / In this paper, we develop a miniaturized real time video compression module (VCM) based on embedded motion JPEG 2000 using ADV212 and FPGA. We consider layout of components, values of damping resistors, and lengths of the pattern lines for optimal hardware design. For software design, we consider compression steps to monitor the status of the system and make the system robust. The weight of the developed VCM is approximately 4 times lighter than the previous development. Furthermore, experimental results show that the PSNR is increased about 3dB and the compression processing time is approximately 2 times faster than the previous development.

No description available.

We present a novel data hiding method for compressed images. The method is designed to minimize the quality loss associated with data embedding into a JPEG image. The described technique uses the objective criterion such as the mean square error and the human visual system based criterion such as the Just Noticable Distortion metric for distortion minimization. The hiding method is designed under the restrictions of the JPEG compression standard to develop new image applications without any modifications or additions to the existing standard. An application example is presented in the thesis. The performance of the technique is examined at different image sizes and resolutions. The cost of hiding in terms of file length extension is examined. Some subjective experiments to determine the zero-perceived distortion hiding capacity are made. An application illustrating the usage of the technique is given. The described application embeds check-bits into JPEG images to facilitate the verification of the sender identity and the authenticity of the transmitted image. In this thesis, we give a list of requirements on the data hiding methods to implement standard compliant applications; design a provably good hiding method operating under these requirements; determine the critical performance points of the method and propose an application based on the method. We have performed some additional research to determine how our system works with high resolution images and existing other well-known algorithms for information hiding. The experiments on high-resolution images have shown that there exists a large embedding capacity for the high resolution images in spite of a loss of embedding density. The performance comparison experiments have shown that the spread spectrum technique offers a competitive but less efficient distortion performance.