Conventional logic circuit designs are based on fully complementary CMOS logic circuits. In the past decade, many Pass-Transistor Logic (PTL) circuits have been proposed that are claimed to have better performance in area, speed and power. Most current PTL logic circuits are composed of a limited number of basic PTL cells (say 2 to 5 types of cells only). However, current placement-and-routing (P&R) CAD tools are mainly designed based on CMOS cell library which usually contains many cells with different logic functions. Thus the P&R tool does not fully exploit the features of the synthesized PTL gate-level netlists. In this thesis, we present a P&R tool dedicated to the generation of the final physical layout for the PTL netlists that are generated from a PTL synthesizer. This backend tool considers the efficient placement and routing of the PTL cells in order to reduce the area cost and to reduce the impact of the interconnection wirings on speed and power performances. Besides, in this thesis, the critical paths of the PTL netlists will be identified and the corresponding input patterns to activate these critical paths will be generated for post-layout speed simulation using HSPICE or Nanosim. In summary, the layout generator in this thesis performs the P&R of PTL netlists and also automatically find the critical paths and their corresponding input patterns.

Vid sifferseriell aritmetik används ett antal parallella bitar för varje siffra. För att jämföra prestanda och effektförbrukning i förhållande till antalet bitar behövde Institutionen för systemteknik (ISY) en layout-generator för att enkelt kunna generera layout för en sifferseriell tvåportsadaptor. Layouten skulle göras i 0.18 mikrometer process. Antalet inkommande databitar och antalet koefficientbitar skulle vara variabelt. Stor vikt lades vid planeringen av layouten för att genereringen av adaptorn skulle fungera smidigt oberoende av de variabla parametrarna. Kod skrevs för att koppla samman layout-instanserna och för att förenkla adaptorn. / Digit serial arithmetics uses a number of parallel bits in each digit. To compare performance and power consumption relative the number of bits, the Department of Electric Engineering (ISY) needed a layout generator to generate layout for a digit serial two-port adaptor. The layout should be done in 0.18 micrometer process. The number of bits of the incoming data and the number of bits of the coefficient should be variable. Great concern was put in the planning of the layout to make the generation of the adaptor work well independent of the parameters. Code was written to connect the layout instances and to simplify the adaptor.

<p>Vid sifferseriell aritmetik används ett antal parallella bitar för varje siffra. För att jämföra prestanda och effektförbrukning i förhållande till antalet bitar behövde Institutionen för systemteknik (ISY) en layout-generator för att enkelt kunna generera layout för en sifferseriell tvåportsadaptor. Layouten skulle göras i 0.18 mikrometer process. Antalet inkommande databitar och antalet koefficientbitar skulle vara variabelt. Stor vikt lades vid planeringen av layouten för att genereringen av adaptorn skulle fungera smidigt oberoende av de variabla parametrarna. Kod skrevs för att koppla samman layout-instanserna och för att förenkla adaptorn. </p> / <p>Digit serial arithmetics uses a number of parallel bits in each digit. To compare performance and power consumption relative the number of bits, the Department of Electric Engineering (ISY) needed a layout generator to generate layout for a digit serial two-port adaptor. The layout should be done in 0.18 micrometer process. The number of bits of the incoming data and the number of bits of the coefficient should be variable. Great concern was put in the planning of the layout to make the generation of the adaptor work well independent of the parameters. Code was written to connect the layout instances and to simplify the adaptor.</p>