With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named Life−timePeakPower management inMixed−Criticalitysystems (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.

A compact device model along with simulations and an experimental analysis of a forward-biasedPNjunction-based silicon Mach-Zehndermodulator (MZM) with a phase-shifter length of 0.5 mm is presented. By placing the PN junction to a certain off-center such that72%of thewaveguide is p-doped, the refractive index swing at a given drive voltage swing is increased by 2% compared to the symmetric layout. The effects of the phase shifters’ length mismatch and asymmetric splitting on the modulation efficiency and extinction ratio of the modulator are simulated and compared with experimental results.Without any pre-emphasis or post-processing, a high-speed operation up to 15 Gb/s using a nonreturn-to-zero modulation format is demonstrated. A modulation efficiency (V πL) as low as 0.07 V × cm is verified and power consumption of 0.88 mW/Gb/s is recorded while a high extinction ratio of 33 dB is experimentally demonstrated. Compared to previously reported forward-biased silicon integrated modulators, without active tuning of the power splitting ratio between the arms, the extinction ratio is 10 dB higher. This MZM along with its compact structure is also sufficiently energy-efficient due to its low power consumption. Thus, it can be suitable for applications like analog signal processing and high-order amplitude modulation transmissions.

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 μ W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 μ W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.