The internet revolution has led to the demand for high speed, low cost solutions for providing high bandwidth to the consumers. Cable and DSL systems address these requirements through sophisticated analog and digital signal processing schemes. A key element of the analog front end of such systems is the line driver which interfaces with the transmission medium such as co-axial cable or twisted pair. The line driver is an amplifier that provides the necessary output current to drive the low impedance of the line. The main requirements for design are high output swing, high linearity, matched impedance to the line and power efficiency. These requirements are addressed by a class AB amplifier whose output impedance can be controlled through feedback. The property of this topology is that when the gain is unity, the output resistance of the driver is matched to the line resistance. Unity gain is achieved for varying line conditions through a tuning loop consisting of peak-to-peak detectors and differential difference amplifier. The design is fabricated in 0.5 micron AMI CMOS process technology. For line variations from 65 to 170 ohms, the gain is unity with an error of 3 % and the impedance matching error is 20 % at the worst-case. The linearity is better than 50 dB for a 1.2 V peak-to-peak signal over the signal bandwidth from 10 kHz to 5 MHz and the line resitance range from 65 to 160 ohms.

In this thesis, the applicability of Class-D amplifiers to integrated wide-band communication line driver applications is studied. While Class-D techniques can address some of the efficiency limitations of linear amplifier structures and have shown promising results in low frequency applications, the low frequency techniques and knowledge need further development in order to improve their practicality for wide band systems. New structures and techniques to extend the application of Class-D to wide-band communication systems, in particular the HomePlug AV wire- line communication standard, will be proposed. Additionally, the digital processing requirements of these wide-band systems drives rapid movement towards nanometer technology nodes and presents new challenges which will be addressed, and new opportunities which will be exploited, for wide-band integrated Class-D line drivers. There are three main contributions of this research. First, a model of Class-D efficiency degradation mechanisms is created, which allows the impact of high-level design choices such as supply voltage, process technology and operating frequency to be assessed. The outcome of this section is a strategy for pushing the high efficiency of Class-D to wide band communication applications, with switching frequencies up to many hundreds of Megahertz. A second part of this research considers the design of efficient, fast and high power Class-D output stages, as these are the major efficiency and bandwidth bottleneck in wide-band applications. A novel NMOS-only totem pole output stage with a fast, integrated drive structure will be proposed. In a third section, a complete wide-band Class-D line driver is designed in a 0.13μm digital CMOS process. The line driver is systematically designed using a rigorous development methodology and the aims are to maximise the achievable signal bandwidth while minimising power dissipation. Novel circuits and circuit structures are proposed as part of this section and the resulting fabricated Class-D line driver test chip shows an efficiency of 15% while driving a 30MHz wide signal with an MTPR of 22dB, at 33mW injected power.

The safety concern of aging aircraft is a rising issue in terms of both safety and cost. An aircraft structure failure during flight is unacceptable. A method needs to be developed and standardized to test the integrity of both commercial and military aircrafts. The current method to test the structure of an aircraft requires the aircraft to be taken out of service for inspection; this is costly due to the inspection required to be performed and the lost use from downtime. A novice idea of an on-site structural health monitoring (SHM) system has been proposed to test the integrity of aircraft structure. An on-site system is a system that can be used to perform inspection on an aircraft simultaneously while the aircraft is in use. This SHM system uses the principles of active lamb wave and passive acoustic emission through the use of piezoelectric sensors as the sensing elements. Piezoelectric sensors can be used both as an input device and as a sensing element. This research focuses on the development of the major data acquisition electronic components of the system. These components are charge amplifier, high pass filter, low pass filter and line driver. A charge amplifier converts a high impedance signal to a low impedance signal. A high pass filter attenuates the low frequency content of a signal, while a low pass filter attenuates the high frequency content of a signal. A line driver converts a low current signal to a high current signal. All of these components need to operate up to a frequency of 2 MHz. Off-the-shelf electronics will be used for prototyping as custom components will not be feasible at this point of the research. / Master of Science

La miniaturisation de circuits intégrés, les hautes fréquences de fonctionnement, la baisse des potentiels d'alimentation, les fortes densités d'intégration rendent les signaux numériques propagés sur les interconnexions très susceptibles à la dégradation voire à la corruption. En vue d’évaluer la compatibilité électromagnétique et l’intégrité du signal il est nécessaire de disposer dès les premières phases de développement de modèles précis de ces interconnexions pour les insérer dans les simulateurs temporels. Nos travaux s'inscrivent dans ce contexte et concernent plus particulièrement la modélisation comportementale des buffers et drivers de ligne de transmission. Ils ont abouti à une approche originale de modélisation notamment basée sur les séries de Volterra-Laguerre. Les modèles boites noires développés disposent d’une implémentation SPICE assez simple autorisant ainsi une très bonne portabilité. Ils sont faciles à identifier et disposent d’une complexité paramétrique permettant un gain important de temps de simulation vis-à-vis des modèles transistors des drivers. En outre les méthodes développées permettent une modélisation dynamique non linéaire plus précise du port de sortie, et une gestion plus générale des entrées autorisant notamment une très bonne prise en compte du régime de sur-cadencement ce que par exemple ne fait pas le standard IBIS. / Integrated circuits miniaturization, high operating frequencies, lower supply voltages, high-density integration make digital signals propagating on interconnects highly vulnerable to degradation. Assessing EMC and signal integrity in the early stages of the design flow requires accurate interconnect models allowing for efficient time-domain simulations. In this context, our work addressed the issue of behavioral modeling of transmission line buffers, and particularly that of drivers. The main result is an original modeling approach partially based on Volterra-Laguerre series. The black box models we developed have a fairly simple implementation in SPICE thus allowing a very good portability. They are easy to identify and have a parametric complexity allowing a large gain in simulation time with respect to transistor driver models. In addition, the developed methods allow a more accurate output port nonlinear dynamics modeling, and a more general management of inputs. A very good reproduction of driver behaviour in overclocking conditions provides a significant advantage over standard IBIS models.

This thesis is concerned with the measurement of physical quantities. Thesis describes sensors in general terms and requirements, which delivers latest trends in the field of automation. The main theme of this thesis is sensors for meassuring pressure, and their connection to the automation chain. In the next part thesis describes the design of the converter for connecting SMART sensors for pressure measuring, that use HART communication protocol, to the automation systems managed by a communication protocol IO-link. First will be described in detail various communication standards by their ISO OSI model, and on this theoretical basis will be based design of converter between communication protocol HART and communication protocol IO-Link. The last part will be Designed software for this converter.