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Design and implementation of an ETSI-SDR OFDM transmitter with power amplifier linearizerJulius, Suranjana 17 September 2010
Satellite radio has attained great popularity because of its wide range of geographical coverage and high signal quality as compared to the terrestrial broadcasts. Most Satellite Digital Radio (SDR) based systems favor multi-carrier transmission schemes, especially, orthogonal frequency division multiplexing (OFDM) transmission because of high data transfer rate and spectral efficiency.
It is a challenging task to find a suitable platform that supports fast data rates and superior processing capabilities required for the development and deployment of the new SDR standards. Field programmable gate array (FPGA) devices have the potential to become suitable development platform for such standards. Another challenging factor in SDR systems is the distortion of variable envelope signals used in OFDM transmission by the nonlinear RF power amplifiers (PA) used in the base station transmitters. An attractive option is to use a linearizer that would compensate for the nonlinear effects of the PA.
In this research, an OFDM transmitter, according to European Telecommunications Standard Institute (ETSI) SDR Technical Specifications 2007-2008, was designed and implemented on a low-cost Xilinx FPGA platform. A weakly nonlinear PA, operating in the L-band SDR frequency (1.450-1.490GHz), was used for signal transmission. An FPGA-based, low-cost, adaptive linearizer was designed and implemented based on the digital predistortion (DPD) reference design from Xilinx, to correct the distortion effects of the PA on the transmitted signal.
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Design and implementation of an ETSI-SDR OFDM transmitter with power amplifier linearizerJulius, Suranjana 17 September 2010 (has links)
Satellite radio has attained great popularity because of its wide range of geographical coverage and high signal quality as compared to the terrestrial broadcasts. Most Satellite Digital Radio (SDR) based systems favor multi-carrier transmission schemes, especially, orthogonal frequency division multiplexing (OFDM) transmission because of high data transfer rate and spectral efficiency.
It is a challenging task to find a suitable platform that supports fast data rates and superior processing capabilities required for the development and deployment of the new SDR standards. Field programmable gate array (FPGA) devices have the potential to become suitable development platform for such standards. Another challenging factor in SDR systems is the distortion of variable envelope signals used in OFDM transmission by the nonlinear RF power amplifiers (PA) used in the base station transmitters. An attractive option is to use a linearizer that would compensate for the nonlinear effects of the PA.
In this research, an OFDM transmitter, according to European Telecommunications Standard Institute (ETSI) SDR Technical Specifications 2007-2008, was designed and implemented on a low-cost Xilinx FPGA platform. A weakly nonlinear PA, operating in the L-band SDR frequency (1.450-1.490GHz), was used for signal transmission. An FPGA-based, low-cost, adaptive linearizer was designed and implemented based on the digital predistortion (DPD) reference design from Xilinx, to correct the distortion effects of the PA on the transmitted signal.
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Development of IS-95 CDMA RF Transceiver Including a Power Amplifier MMIC DesignWang, Shi-Ming 04 July 2001 (has links)
Abstract¡G
This thesis was consisted of two parts. Part 1 introduced the procedure for designing the RF transceiver module in an IS-95 CDMA system using link budget analysis. Part 2 was focused on a CDMA power amplifier integrated circuit design for Personal Communication Service (PCS) applications. The design procedure was introduced in detail and implemented in MMIC for using GaAs HBT foundry provided by the GCS Ltd.. The designed linear gain, output 1dB compression point and power added efficiency (PAE) are above 30 dB, 27 dBm and 36.7% respectively under a single supply voltage of 3.4 V with the help of a diode linearizer. Harmonic components were suppressed more than 26 dB without use of any filters in the output. The adjacent channel power ratio (ACPR) and the VSWR of input port are below -45 dBc and 2 respectively.
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