Abstract¡G This thesis was consisted of two parts. Part 1 introduced the procedure for designing the RF transceiver module in an IS-95 CDMA system using link budget analysis. Part 2 was focused on a CDMA power amplifier integrated circuit design for Personal Communication Service (PCS) applications. The design procedure was introduced in detail and implemented in MMIC for using GaAs HBT foundry provided by the GCS Ltd.. The designed linear gain, output 1dB compression point and power added efficiency (PAE) are above 30 dB, 27 dBm and 36.7% respectively under a single supply voltage of 3.4 V with the help of a diode linearizer. Harmonic components were suppressed more than 26 dB without use of any filters in the output. The adjacent channel power ratio (ACPR) and the VSWR of input port are below -45 dBc and 2 respectively.

abstract: Due to high level of integration in RF System on Chip (SOC), the test access points are limited to the baseband and RF inputs/outputs of the system. This limited access poses a big challenge particularly for advanced RF architectures where calibration of internal parameters is necessary and ensure proper operation. Therefore low-overhead built-in Self-Test (BIST) solution for advanced RF transceiver is proposed. In this dissertation. Firstly, comprehensive BIST solution for RF polar transceivers using on-chip resources is presented. In the receiver, phase and gain mismatches degrade sensitivity and error vector magnitude (EVM). In the transmitter, delay skew between the envelope and phase signals and the finite envelope bandwidth can create intermodulation distortion (IMD) that leads to violation of spectral mask requirements. Characterization and calibration of these parameters with analytical model would reduce the test time and cost considerably. Hence, a technique to measure and calibrate impairments of the polar transceiver in the loop-back mode is proposed. Secondly, robust amplitude measurement technique for RF BIST application and BIST circuits for loop-back connection are discussed. Test techniques using analytical model are explained and BIST circuits are introduced. Next, a self-compensating built-in self-test solution for RF Phased Array Mismatch is proposed. In the proposed method, a sinusoidal test signal with unknown amplitude is applied to the inputs of two adjacent phased array elements and measure the baseband output signal after down-conversion. Mathematical modeling of the circuit impairments and phased array behavior indicates that by using two distinct input amplitudes, both of which can remain unknown, it is possible to measure the important parameters of the phased array, such as gain and phase mismatch. In addition, proposed BIST system is designed and fabricated using IBM 180nm process and a prototype four-element phased-array PCB is also designed and fabricated for verifying the proposed method. Finally, process independent gain measurement via BIST/DUT co-design is explained. Design methodology how to reduce performance impact significantly is discussed. Simulation and hardware measurements results for the proposed techniques show that the proposed technique can characterize the targeted impairments accurately. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

This thesis consisted of three parts. Part 1 introduced the design procedure of an RF transceiver modules for IEEE 802.11b WLAN system. It contained the selection of RF architectures, frequency planning, and the receiver link budget analysis flow. Part 2 focused on the implementation of each stage in the whole RF link. The design considerations of choosing passive elements and the parasitic effect of the evaluation board are discussed. Part 3 integrated the whole RF transceiver module and estimated the performance of this module through the link budget analysis method. Furthermore, a complete specification measurement was accomplished by using the standard test signals. The test results confirmed with the budget results, and also pass the specification of IEEE 802.11b WLAN system.

Wireless body area networks (WBANs) have tremendous potential to benefit from wireless communication technology and are expected to make sweeping changes in the future human health care and medical fields. While the prospects for WBAN products are high, meeting required device performance with a meager amount of power consumption poses significant design challenges. In order to address these issues, IEEE has recently developed a draft of IEEE 802.15.6 standard dedicated to low bit-rate short-range wireless communications on, in, or around the human body. Commercially available SoC (System-on-Chip) devices targeted for WBAN applications typically embed proprietary wireless transceivers. However, those devices usually do not meet the quality of service (QoS), low power, and/or noninterference necessary for WBAN applications, nor meet the IEEE standard specifications. This dissertation presents a design of low-power RF front-end conforming to the IEEE standard in Medical Communication Service (MICS) band of 402-405 MHz. First, we investigated IEEE 802.15.6 PHY specifications for narrow band WBAN applications. System performance analysis and simulation for an AWGN (additive white Gaussian noise) channel was conducted to obtain the BER (bit error rate) and the PER (packet error rate) as the figure of merit. Based on the system performance study, the link budget was derived as a groundwork for our RF front-end design. Next, we examined candidate RF front-end architectures suitable for MICS applications. Based on our study, we proposed to adopt a direct conversion transmitter and a low-IF receiver architecture for the RF front-end. An asynchronous wake-up receiver was also proposed, which is composed of a carrier sensing circuit and a serial code detector. Third, we proposed and implemented low-power building blocks of the proposed RF front-end. Two quadrature signal generation techniques were proposed and implemented for generation of quadrature frequency sources. The two quadrature voltage controlled oscillators (QVCOs) were designed using our proposed current-reuse VCO with two damping resistors. A stacked LNA and a down-conversion mixer were proposed for low supply and low power operation for the receiver front-end. A driver amplifier and an up-conversion mixer for the transmitter front-end were implemented. The proposed driver amplifier uses cascaded PMOS transistors to minimize the Miller effect and enhance the input/output isolation. The up-conversion mixer is based on a Gilbert cell with resistive loads. Simulation results and performance comparisons for each designed building block are presented. Finally, we present a case study on a direct VCO modulation transmitter and a super-regenerative receiver, which can also be suitable for an MICS transceiver. Several crucial building blocks including a digitally-controlled oscillator (DCO) and quench signal generators are proposed and implemented with a small number of external components. / Ph. D.

La bande de fréquence non-licensée autour de 60 GHz est une alternative prometteuse pour couvrir les besoins en bande passante des futurs systèmes de communication. L'utilisation de modulations complexes (comme OFDM ou 64-QAM) à ces fréquences permet d'atteindre, en utilisant une technologie CMOS standard, des débits de plusieurs gigabits par seconde sur quelques mètres voire quelques dizaines de mètres. Pour atteindre ces performances, la tête d'émission-réception RF (front-end RF) doit être dotée d'une référence de fréquence haute performance. Dans ce travail, une architecture originale est proposée pour générer cette référence de fréquence haute performance. Elle repose sur la multiplication de fréquence d'ordre élevé (plusieurs dizaines) d'un signal de référence basse fréquence (moins de quelques GHz), tout en recopiant les propriétés spectrales du signal basse fréquence. Cette multiplication est réalisée en combinant la production d'un signal multi-harmonique dont la puissance est concentrée autour de la fréquence à synthétiser. L'harmonique d'intérêt est ensuite extraite au moyen d'un filtrage. Ces deux étapes reposent sur l'utilisation d'oscillateurs dans des configurations spécifiques. Ce travail porte à la fois sur la mise en équation et l'étude du fonctionnement de ce système, et sur la conception de circuits dans des technologies CMOS avancées (CMOS 40 nm, BiCMOS 55 nm). Les mesures sur les circuits fabriqués permettent de valider la preuve de concept ainsi que de montrer des performances à l'état de l'art. L'étude du fonctionnement de ce système a conduit à la découverte d'une forme particulière de synchronisation des oscillateurs ainsi qu'à l'expression de solutions approchées de l'équation de Van der Pol dans deux cas pratiques particuliers. Les perspectives de ce travail sont notamment l'intégration de cette synthèse innovante dans un émetteur-récepteur complet. / The 60-GHz unlicensed band is a promising alternative to perform the high data rate required in the next generation of wireless communication systems. Complex modulations such as OFDM or 64-QAM allow reaching multi-gigabits per second throughput over up to several tens of meters in standard CMOS technologies. This performance rely on the use of high performance millimeter-wave frequency synthesizer in the RF front-end. In this work, an original architecture is proposed to generate this high performance millimeter-wave frequency synthesizer. It is based on a high order (several tens) multiplication of a low frequency reference (few GHz), that is capable of copying the low frequency reference spectral properties. This high order frequency multiplication is performed in two steps. Firstly, a multi-harmonic signal which power is located around the harmonic of interest is generated from the low frequency reference signal. Secondly, the harmonic of interest is filtered out from this multi-harmonic signal. Both steps rely on the specific use of oscillators. This work deals with the circuit design on advanced CMOS technologies (40 nm CMOS, 55 nm BiCMOS) for the proof of concept and on the theoretical study of this system. This novel technique is experimentally validated by measurements on the fabricated circuits and exhibit state-of-the-art performance. The analytical study of this high order frequency multiplication led to the discovery of a particular kind of synchronization in oscillators and to approximated solutions of the Van der Pol equation in two different practical cases. The perspectives of this work include the design of the low frequency reference and the integration of this frequency synthesizer in a complete RF front-end architecture.

L'Internet des objets (IoT) est annoncé comme la prochaine grande révolution technologique où des milliards d'appareils s'interconnecteront en utilisant les technologies d’Internet et permettront aux utilisateurs d'interagir avec le monde physique, permettant Smart Home, Smart Cities, tout intelligent. Les réseaux de capteurs sans fil (WSN) sont cruciales pour tourner la vision de l'IoT dans une réalité, mais pour que cela devienne réalité, beaucoup de ces dispositifs doivent être autonomes en énergie. Par conséquent, un défi majeur est de fournir une durée de vie de plusieurs années tout en alimentant les nœuds par batteries ou en utilisant l'énergie récoltée. Bluetooth Low Energy (BLE) a montré une efficacité énergétique et une robustesse supérieures à celles d'autres protocoles WSN bien connus, ce qui fait BLE un candidat solide pour la mise en œuvre dans des scénarios IoT. En outre, BLE est présent dans presque tous les smartphones, ce qui en fait une télécommande universelle omniprésente pour les maisons intelligentes, les bâtiments ou les villes. Néanmoins, l'amélioration de la performance BLE pour les cas typiques d'utilisation de l'IoT, où la durée de vie de la batterie de nombreuses années, est toujours nécessaire.Dans ce travail, nous avons évalué les performances de BLE en termes de latence et de consommation d'énergie sur la base de modèles analytiques afin d'optimiser ses performances et d'obtenir son niveau maximal d'efficacité énergétique sans modification de la spécification en premier lieu. À cette fin, nous avons proposé une classification des scénarios ainsi que des modes de fonctionnement pour chaque scénario. L'efficacité énergétique est atteinte pour chaque mode de fonctionnement en optimisant les paramètres qui sont affectés aux nœuds BLE pendant la phase de découverte du voisin. Cette optimisation des paramètres a été réalisée à partir d'un modèle énergétique extrait de l'état de la technique. Le modèle, à son tour, a été optimisé pour obtenir une latence et une consommation d'énergie quel que soit le comportement des nœuds à différents niveaux: application et communication. Puisqu'un nœud peut être le périphérique central à un niveau, alors qu'il peut être le périphérique à l'autre niveau en même temps, ce qui affecte la performance finale des nœuds.En outre, un nouveau modèle d'estimation de la durée de vie de la batterie a été présenté pour montrer l'impact réel de l'optimisation de la consommation énergétique sur la durée de vie des nœuds, de façon rapide (en termes de temps de simulation) et réaliste (en tenant compte des données empiriques). Les résultats de performance ont été obtenus dans notre simulateur Matlab basé sur le paradigme OOP, à travers l'utilisation de plusieurs cas de test IoT. En outre, le modèle de latence utilisé pour notre étude a été validé expérimentalement ainsi que l'optimisation des paramètres proposée, montrant une grande précision.Après avoir obtenu les meilleures performances possibles de BLE sans modification de la spécification, nous avons évalué les performances du protocole en implémentant le concept de Wake-Up radio (WuR), qui est un récepteur d’ultra-faible consommation et qui est en charge de détecter le canal de communication, en attente d'un signal adressé au nœud, puis réveiller la radio principale. Ainsi, la radio principale, qui consomme beaucoup plus d'énergie, peut rester en mode veille pendant de longues périodes et passer en mode actif uniquement pour la réception de paquets, économisant ainsi une quantité d'énergie considérable. Nous avons démontré que la durée de vie de BLE peut être significativement augmentée en implémentant une WuR et nous proposons une modification du protocole afin de rendre ce protocole compatible avec un mode de fonctionnement qui inclut une WuR. Pour cela, nous avons étudié l'état de l'art de la WuR et évalué la durée de vie des périphériques BLE lorsqu'une WuR sélectionnée est implémentée du côté master. / The Internet of Things (IoT) is announced as the next big technological revolution where billions of devices will interconnect using Internet technologies and let users interact with the physical world, allowing Smart Home, Smart Cities, smart everything. Wireless Sensor Network (WSN) are crucial for turning the vision of IoT into a reality, but for this to come true, many of these devices need to be autonomous in energy. Hence, one major challenge is to provide multi-year lifetime while powered on batteries or using harvested energy. Bluetooth Low Energy (BLE) has shown higher energy efficiency and robustness than other well known WSN protocols, making it a strong candidate for implementation in IoT scenarios. Additionally, BLE is present in almost every smartphone, turning it into perfect ubiquitous remote control for smart homes, buildings or cities. Nevertheless, BLE performance improvement for typical IoT use cases, where battery lifetime should reach many years, is still necessary.In this work we evaluated BLE performance in terms of latency and energy consumption based on analytical models in order to optimize its performance and obtain its maximum level of energy efficiency without modification of the specification in a first place. For this purpose, we proposed a scenarios classification as well as modes of operation for each scenario. Energy efficiency is achieved for each mode of operation by optimizing the parameters that are assigned to the BLE nodes during the neighbor discovery phase. This optimization of the parameters was made based on an energy model extracted from the state of the art. The model, in turn, has been optimized to obtain latency and energy consumption regardless of the behavior of the nodes at different levels: application and communication. Since a node can be the central device at one level, while it can be the peripheral device at the other level at the same time, which affects the final performance of the nodes.In addition, a novel battery lifetime estimation model was presented to show the actual impact that energy consumption optimization have on nodes lifetime in a fast (in terms of simulation time) and realistic way (by taking into account empirical data). Performance results were obtained in our Matlab based simulator based on OOP paradigm, through the use of several IoT test cases. In addition, the latency model used for our investigation was experimentally validated as well as the proposed parameter optimization, showing a high accuracy.After obtaining the best performance possible of BLE without modification of the specification, we evaluated the protocol performance when implementing the concept of Wake-Up radio, which is an ultra low power receiver in charge on sensing the communication channel, waiting for a signal addressed to the node and then wake the main radio up. Thus, the main radio which consumes higher energy, can remain in sleep mode for long periods of time and switch to an active mode only for packet reception, therefore saving considerable amount of energy. We demonstrated that BLE lifetime can be significantly increased by implementing a Wake-Up radio and we propose a modification of the protocol in order to render this protocol compatible with an operating mode which includes a Wake-Up radio. For this, we studied the Wake-Up radio state of the art and evaluated BLE devices lifetime when a selected Wake-Up radio is implemented at the master side.

This project investigates developing and implementing innovative indoornavigation systems by leveraging repurposed Wi-Fi infrastructure anddedicated RFM69HCW transceivers. Aimed at enhancing indoor positioningaccuracy, the study explores the viability of using Received Signal StrengthIndicator (RSSI) and dedicated device localization techniques to overcomethe limitations of existing Global Positioning System (GPS) technology inindoor environments. Through the design and testing of a printed circuit board(PCB) prototype that connects Raspberry Pi Pico (RPP) to RFM69HCWmodules and the development of custom drivers for the RP2040 processor,this research addresses the challenges of indoor navigation, such as signalvariability and environmental interference. The project also emphasizes theimportance of sustainable technology development by repurposing electronicwaste for innovative applications. Findings from the study reveal the potentialof these methodologies to improve indoor positioning accuracy despitechallenges related to hardware compatibility and the dynamic nature of indoorspaces. This research contributes to indoor navigation by demonstrating thefeasibility of using repurposed and dedicated hardware solutions, offeringinsights into future directions for enhancing indoor navigation systems, andhighlighting the role of sustainability in technological innovation.