The new family of Field Programmable Gate Arrays, CLI 6000 from Concurrent Logic Inc realizes truly Cellular Logic. It has been mainly designed for the realization of data path architectures. However, the realizable logic functions provided by its macrocells and their limited connectivity call also for new general-purpose logic synthesis methods. The basic cell of CLi 6000 can be programmed to realize a two-input multiplexer ( A*B + C*B ), an AND/EXOR cell ( A*B Ea C ), or the basic 2-input AND, OR and EXOR gate. This suggests to using these cells for tree-like expansions. These "cellular logic" devices require regular connection patterns in the netlists resulting from logic synthesis. This thesis presents a synthesis tree searching program PROMPT, which generates AND/EXOR tree circuits from given Boolean functions. Such circuits have the property that the gate structures are AND/EXOR ( A *B EB C ), AND and EXOR which could be realized by the CLI6000 cells. Also, the connection. way in the circuit is that usually the output of one level gate is the input of the next level gate of the tree. This matches ideally to the architecture of the CLI6000 bussing network where the macrocells have only connections to their neighboring cells. PROMPT is based on the Davio expansions ( an equivalent of the Shannon expansions for the EXOR gates ) as its Boolean decomposition methods. The program includes three versions: exact version, heuristic version and fixed-variable version. The exact version of PROMPT generates the Permuted Reed-Muller Tree circuit which has the minimum number of gates. Such tree circuit is obtained by searching through all possible combinations of the expansion variable orders to get the one which needs the least number of gates. The heuristic version of PROMPT is designed to decrease the time complexity of the search algorithm when dealing with logic functions having many input variables. It generates a Permuted Reed-Muller Tree which may not have the minimum number of gates. However, the tree searching time in this version decreases tremendously compared to the time necessary in the exact version. The fix-variable version is developed to generate Reed-Muller Tree circuits. Such circuits will have the same expansion variables at the same tree level, so they can be easier routed after the placement to the CLI6000 chips. In short, the program PROMPT generates the PRM and RM tree circuits which are particularly well matched to both the realization of logic cell and connection structure of the CLI6000 device. Thus, the PRM and RM circuits can be easily placed and routed on the CLI6000 FPGAs.

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 134-144). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--Ohio University, August, 2002. / Title from PDF t.p.

Thesis (M.S.)--Ohio University, August, 1999. / Title from PDF t.p.

Thesis (MEng)--University of Stellenbosch, 2000. / ENGLISH ABSTRACT: The need for a locally manufactured, cost-effective, fuel management system led to the design and development of a functional prototype. This thesis presents the design, development and full implementation of two functional prototypes. While field tests performed on the first prototype assisted in identifying necessary modifications, a need for greater complexity in support hardware was also identified. In order to comply with the cost-effective nature of the project, it was realized that this complexity could only be achieved via the implementation of a CPLD based system. Using Altera's Maxplus II design software, the CPLD code was synthesized according to the required specifications then simulated and analyzed On completion of the new CPLD based system, the second prototype, one of Altera's megacore functions is implemented and used as a substitute to an external hardware. All necessary modifications were successfully completed and the system was installed. / AFRIKAANSE OPSOMMING: Die benodiging van 'n lokale vervaardigde, koste effektiewe brandstofbeheerstelsel het gelei tot die ontwerp en ontwikkeling van 'n funksionele prototipe. Hierdie tesis dek die ontwerp, ontwikkeling en volle implementasie van twee funksionele prototipes. Terwyl toetse op die eerste prototipe gebruik is om die nodige aanpassings te identifiseer, is daar ook besef dat daar meer komplekse hardeware onderstuening benodig word. Om die koste effektiewe aard van die projek te handhaaf, is daar gesien dat die nodige kompleksieteit alleenlik deur middel van die implementering van 'n 'CPLD' gebaseerde sisteem bereik kan word. Deur gebruik te maak van Altera se Maxplus II ontwerp sagteware, is die 'CPLD' kode met die nodige spesifiekasies gesintiseer, gesimuleer en geanaliseer. Na voltooing van die tweede prototiepe, die 'CPLD' gebaseerde sisteem, is een van Altera se megacore funksies geimplementeer en gebruik as 'n plaasvervanger vir eksteme hardware. AIle nodige aanpassings is suksesvol voltooi en die sisteem is geinstalleer.

O uso de pequenos satélites tem aumentado substancialmente nos últimos anos devido ao custo reduzido de desenvolvimento e lançamento, assim como pela flexibilidade oferecida pela utilização de componentes comerciais. Este trabalho propõe o projeto e a implementação de uma plataforma para teste, controle e qualificação de circuitos integrados (Integrated Circuits, CIs) comerciais e customizados para uso em aplicações espaciais. Esta plataforma flexível pode ser ajustada a uma gama de dispositivos e interfaces, e reduz os esforços de integração desses componentes e, portanto, acelera o desenvolvimento de todo o projeto. O sistema proposto é sintetizado em um tecnologia de Arranjo de Portas Programáveis em Campo (Field Programmable Gate Array) baseado em memória Flash, que, apesar de não ser classificado para uso aeroespacial, testes demonstram a viabilidade de seu uso. Este sistema adaptável permite o controle de novas cargas-úteis e softcores para o teste e validação antes da sua aplicação em voo. A comunicação com dispositivos é feita através de protocolos préimplementados. Os resultados de testes funcionais in loco sugerem a possibilidade de aplicação desta plataforma para uso em Cubesats. A primeira aplicação desta plataforma foi no teste do controle da placa de carga-útil do NanoSatC-BR1, o primeiro nanossatélite científico brasileiro, lançado em órbita em 2014. / The number of small satellites has substantially increased in the last years due to reduced development and launching costs, as well as due to the flexibility brought by the usage of commercial off the shelf components. This work purposes the design and implementation of a platform for test, control and qualification of commercial and customized integrated circuits for space applications. This flexible platform can be adjusted to control a wide range of devices and interfaces, and is intended to reduce the integration difficulties, resulting in the speed up of some of the project stages. The platform is synthesized in a Flash-based Field Programmable Gate Array technology. The target device is not qualified for aerospace projects. Nevertheless, previous radiation tests demonstrated its hardness for space missions. The system is adaptable and makes it possible to control, test and validate new payloads and softcores before flight. The communication between devices is done through pre-implemented protocols. Functional tests suggested the possibility to apply the platform in Cubesats projects. The first application of this platform was in the NanoSatC-BR1, the first Brazilian scientific nanosatellite, to test the controller of the payload board.

O uso de pequenos satélites tem aumentado substancialmente nos últimos anos devido ao custo reduzido de desenvolvimento e lançamento, assim como pela flexibilidade oferecida pela utilização de componentes comerciais. Este trabalho propõe o projeto e a implementação de uma plataforma para teste, controle e qualificação de circuitos integrados (Integrated Circuits, CIs) comerciais e customizados para uso em aplicações espaciais. Esta plataforma flexível pode ser ajustada a uma gama de dispositivos e interfaces, e reduz os esforços de integração desses componentes e, portanto, acelera o desenvolvimento de todo o projeto. O sistema proposto é sintetizado em um tecnologia de Arranjo de Portas Programáveis em Campo (Field Programmable Gate Array) baseado em memória Flash, que, apesar de não ser classificado para uso aeroespacial, testes demonstram a viabilidade de seu uso. Este sistema adaptável permite o controle de novas cargas-úteis e softcores para o teste e validação antes da sua aplicação em voo. A comunicação com dispositivos é feita através de protocolos préimplementados. Os resultados de testes funcionais in loco sugerem a possibilidade de aplicação desta plataforma para uso em Cubesats. A primeira aplicação desta plataforma foi no teste do controle da placa de carga-útil do NanoSatC-BR1, o primeiro nanossatélite científico brasileiro, lançado em órbita em 2014. / The number of small satellites has substantially increased in the last years due to reduced development and launching costs, as well as due to the flexibility brought by the usage of commercial off the shelf components. This work purposes the design and implementation of a platform for test, control and qualification of commercial and customized integrated circuits for space applications. This flexible platform can be adjusted to control a wide range of devices and interfaces, and is intended to reduce the integration difficulties, resulting in the speed up of some of the project stages. The platform is synthesized in a Flash-based Field Programmable Gate Array technology. The target device is not qualified for aerospace projects. Nevertheless, previous radiation tests demonstrated its hardness for space missions. The system is adaptable and makes it possible to control, test and validate new payloads and softcores before flight. The communication between devices is done through pre-implemented protocols. Functional tests suggested the possibility to apply the platform in Cubesats projects. The first application of this platform was in the NanoSatC-BR1, the first Brazilian scientific nanosatellite, to test the controller of the payload board.

A morfologia matemática é o estudo da forma utilizando as ferramentas da teoria de conjuntos e representa uma área extremamente importante em análise de imagens. Suas operações básicas são a dilatação e a erosão, e através destas é possível realizar outras operações mais complexas. A morfologia matemática fornece ferramentas poderosas para a realização de análise de imagens em baixo nível e tem encontrado aplicações em diversas áreas, tais como: visão robótica, inspeção visual, medicina, análise de textura, entre outras. Muitas destas aplicações requerem processamento em tempo real, e para sua execução de forma eficiente freqüentemente é utilizado hardware dedicado. A análise de imagens em baixo nível geralmente envolve computações repetidas sobre estruturas grandes de dados. Assim, o paralelismo parece ser um atributo necessário de um sistema de hardware capaz de executar eficientemente estas tarefas. As ferramentas da morfologia matemática são bem adequadas à implementação em arquiteturas pipeline. A necessidade de sistemas capazes de realizar o processamento de imagens digitais em tempo real, com o menor custo e tempo de desenvolvimento, tem sido suprida pela tecnologia de dispositivos de lógica programável complexa. Assim, neste trabalho foi projetada e implementada uma arquitetura pipeline dedicada para dilatação e erosão de imagens binárias em tempo real utilizando dispositivos lógicos programáveis de alta capacidade. Esta arquitetura é capaz de processar imagens binárias de 512 x 512 pixels. Os estágios desta arquitetura são flexíveis, permitindo a reprogramação da forma e do tamanho dos elementos estruturantes utilizados nas operações morfológicas. A arquitetura desenvolvida apresentou um desempenho satisfatório, demonstrando ser uma alternativa viável e eficiente. / Mathematical morphology is a very important image analysis area that uses set theory tools to study shapes. The basic operations in mathematical morphology are dilation and erosion, these can be used for more complex operations. Mathematical morphology has powerful tools for low level image processing and has been used in a wide range of applications such as robotic vision, visual inspection, medicine and texture analysis. Low level image processing requires repetitive processing over large data structures, dedicated parallel computing hardware is often used. Complex field programmable logic devices (CPLDs) have increasingly been used for the fast development of real time image processing systems. In this work we present a pipeline architecture for real time erosion and dilation operations, the architecture was developed using high density programmable logic devices. The developed architecture can process 512 x 512 pixels binary images, and has flexible stages that can be reprogrammed according to the shape and size of the structuring elements used in the morphological operations. Tests performed using the architecture demonstrated its good performance and that it is a good and efficient alternative for dedicated morphological image processing operations.

Um sistema que realiza a detecção de movimento procura, numa seqüência de imagens, sinais que confirmem a existência de movimentação no ambiente monitorado. Uma vez realizada a detecção do movimento, pode-se realizar o rastreamento (tracking) do objeto na cena em questão. A detecção e o rastreamento de objetos, em tempo real, são técnicas que estão despertando grande interesse por parte de pesquisadores e empresas pois, estas técnicas, podem ser utilizadas em diversas áreas que se estendem desde a engenharia e computação até áreas como a geologia e medicina. Sendo assim, seguindo-se a idéia básica de detecção e rastreamento, encontram-se diversas aplicações para estas técnicas como: sistemas de vigilância, análise de movimentos humanos, sistemas de detecção e rastreamento de pedestres ou veículos, dentre outras. Neste trabalho é mostrado um sistema que foi desenvolvido para armazenamento de imagens em tons de cinza de uma seqüência de vídeo e um posterior processamento dessas imagens para detecção de características que indiquem movimento. O processamento se resume em integrar o sinal de vídeo, que está armazenado nas memórias, nas direções horizontal e vertical gerando os histogramas de intensidade horizontal e vertical. Comparando os histogramas de quadros diferentes da seqüência de vídeo será possível detectar a presença de movimento e a região da imagem onde este ocorreu. Devido à necessidade de um processamento rápido das imagens e no interesse de produzir um sistema dedicado com hardware reduzido, utilizou-se de dispositivos de lógica programável complexa (CPLDs). / A system that performs movement detection in a sequence of images looks for signs that confirm the occurrence of the movement in the controlled environment. Once the movement of the object is detected it is possible to perform the tracking of the object. Real time object detection and tracking techniques are of great interests to researchers and industries because these techniques can be used in several areas going from engineering and computing to geology and medicine. There is a wide field of applications of detection and tracking techniques, such as: surveillance systems, human movement analysis, pedestrians or vehicle detection. This work presents an implementation able to store a gray level image from a video sequence and from these images detect in real time a object movement in the scene. The detection will be performed integrating an image from the video sequence in the horizontal and vertical directions in order to obtain the intensities histograms in these directions. Comparing the histograms with those of a different frame of the video sequence it will be possible to detect the presence of movement and locate where in the image the movement occurs. Due to real time digital image processing requirements and in order to produce a reduce dedicated hardware, complex programmable logic devices (CPLDs) were used.

D.Phil. (Electrical and Electronic Engineering) / Load forecasting is a necessary and an important task for both the electrical consumer and electrical supplier. Whilst many studies emphasize the importance of determining the future demand, few papers address both the forecasting algorithm and computational resources needed to offer a turnkey solution to address the load forecasting problem. The major contribution that, this paper identified is a turnkey load forecasting algorithm. A turnkey forecasting solution is defined by a comprehensive solution that incorporates both the algorithm and processing elements needed to execute the algorithm in the most effective and efficient manner. An electrical consumer, namely the operator of a rapid railway system was faced with a problem of having to forecast the notified network demand and energy consumption. The forecast period was expected to be between a very short term window for maintenance reasons and long term for the requirements warranted by the electrical supplier. The problem was addressed by firstly reviewing the most common forms of load forecasting for which there are two types. These are statistically based methods and methods based upon artificial intelligence. The basic principle of a statistical approach is to approximate or define a curve that best defines the relationship between the load and its parameters. Regression and similar day approach methods use the defined correlation of past values in order to forecast the future behaviour. In other words the future load forecast is forecasted by observing the behaviour of the factors that influenced the load behaviour in the past. The underlying factors that influence the final load may be identified by means of a top down drill down approach. In this way both the load factors and influential variables may be identified. This paper makes use of relevance trees to create a structure of load and influential variables. For a regression forecasting model, the behaviour of the load is modelled according to weather and non-weather variables. The load may be stochastic or deterministic, linear or nonlinear. One of the biggest problems with statistical models is the lack of generality. One model may yield more acceptable results over another model simply because of the sensitivity of the model to one load element that defines the model significantly. Regression type forecast models are an example of this where the elements that define the load are broadly divided into weather and non-weather elements. It is important that the correlation curve reflects the true correlation between the load and its elements. The recursive properties of a statistical based techniques (Kalman filter) allows that the relationship be refined. For methods such as neural networks, the relationship between the load elements that define the future load behaviour is learnt by presenting a series of patterns and then a forecast model is derived. Rigorous mathematical equations are replaced with an artificial neural network where the load curve is learnt. Unlike a statistical based approach (ARMA models), the load does not first need to be defined as a stochastic or deterministic series. In terms of a stochastic approach (non stationery process), the load first would have to be brought to a stationery process. For artificial neural networks, such processes are eliminated and the future forecast is derived faster in terms of a turnkey approach (tested solution). Artificial Neural Networks (ANN) has gained momentum since the eighties. Specifically in the area of forecasting, neural networks have become a common application. In this thesis, data from a railway operator was used to train the neural network and then future data is forecasted. Two embedded processing elements were then evaluated in terms of speed, memory and ability to execute complex mathematical functions (libraries). These were namely a Complex Programmable Logic Device (CPLD) and microcontroller (MCU). The ANN forecasting algorithm was programmed on both a MCU and PLD and compared by means of timing models and hardware platform testing. The most ideal turnkey solution was found to be the ANN algorithm residing on a PLD. The accuracy and speed results surpassed that of a MCU.