Sinusoidal oscillator is intensively used in many applications, such as built-in-self-testing and ADC characterization. An innovative medical application for skin cancer detection employed a technology named bio-impedance spectroscopy, which also requires highly linear sinusoidal-wave as the reference clock. Moreover, the generated sinusoidal signals should be tunable within the frequency range from 10kHz to 10MHz, and quadrature outputs are demanded for coherent demodulation within the system. A design methodology of sinusoidal oscillator named digital-harmonic-cancellation (DHC) technique is presented. DHC technique is realized by summing up a set of square-wave signals with different phase shifts and different summing coefficient to cancel unwanted harmonics. With a general survey of literature, some sinusoidal oscillators based on DHC technique are reviewed and categorized. Also, the mathematical algorithm behind the technique is explained, and non-ideality effect is analyzed based on mathematical calculation. The prototype is fabricated in OnSemi 0.5um CMOS technology. The experimental results of this work show that it can achieve HD2 is -59.74dB and HD3 is -60dB at 0.9MHz, and the frequency is tunable over 0.1MHz to 0.9MHz. The chip consumes area of 0.76mm2, and power consumption at 0.9MHz is 2.98mW. Another design in IBM 0.18um technology is still in the phase of design. The preliminary simulation results show that the 0.18um design can realize total harmonic distortion of -72dB at 10MHz with the power consumption of 0.4mW. The new design is very competitive with state-of-art, which will be finished with layout, submitted for fabrication and measured later.

Optimizing a modulator driver for linear and high-speed operation, while simultaneously achieving a high output voltage swing is very challenging. This paper investigates the design of a highlylinear, high-bandwidth yet power-efficient Mach-Zehnder modulator driver based on the breakdown voltage doubler concept, which overcomes the transistors' physical limitations and enables output voltage swings twice as high as conventional differential pair amplifiers can provide. The low-power design was enabled by the use of an open-collector topology for the output stage as well as by employing resistors instead of current mirrors in order to provide the bias currents for the emitter-follower (EF) stages. We show that by means of this EF implementation approach, the power consumption can be reduced by 19% without sacrificing the circuit's bandwidth and linearity. The driver achieves peak-to-peak differential output voltage swings above 6.5 Vpp,d and consumes 670mWof DC power, being one of the most power-efficient drivers in the literature. The 3-dB bandwidth is 61.2 GHz and the total harmonic distortion is 1%, measured at 1 GHz and for the output swing of 6.5 Vpp,d. To the best of the authors' knowledge, these are the highest linearity and output voltage swing reported in the literature for modulator drivers with bandwidths above 40 GHz.