This thesis employs computational and experimental methods to explore hotspot cooling and high heat flux removal from a 3-D stacked chip using thermoelectric and microfluidic devices. Stacked chips are expected to improve microelectronics performance, but present severe thermal management challenges. The thesis provides an assessment of both thermoelectric and microfluidic technologies and provides guidance for their implementation in the 3-D stacked chips. A detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. The numerical analysis suggests that TECs can be used for on demand cooling of hotspots in 3-D stacked chip architecture. A strong vertical coupling is observed between the top and bottom TECs and it is found that the bottom TECs can detrimentally heat the top hotspots. As a result, TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between the TEC and heat spreader are shown to significantly affect TEC performance. TECs are most effective for cooling localized hotspots, but microchannels are advantageous for cooling large background heat fluxes. In the present work, the results of heat transfer and pressure drop experiments in the microchannels with water as the working fluid are presented and compared to the previous microchannel experiments and CFD simulations. Heat removal rates of greater than 100 W/cm2 are demonstrated with these microchannels, with a pressure drop of 75 kPa or less. A novel empirical correlation modeling method is proposed, which uses finite element modeling to model conduction in the channel walls and substrate, coupled with an empirical correlation to determine the convection coefficient. This empirical correlation modeling method is compared to resistor network and CFD modeling. The proposed modeling method produced more accurate results than resistor network modeling, while solving 60% faster than a conjugate heat transfer model using CFD. The results of this work demonstrate that microchannels have the ability to remove high heat fluxes from microelectronic packages using water as a working fluid. Additionally, TECs can locally cool hotspots, but must be carefully placed to avoid undesired heating. Future work should focus on overcoming practical challenges including fabrication, cost, and reliability which are preventing these technologies from being fully leveraged.

Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of >100W/cm² of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm².

A stacked microchannel heat sink was developed to provide efficient cooling for microelectronics devices at a relatively low pressure drop while maintaining chip temperature uniformity. Microfabrication techniques were employed to fabricate the stacked microchannel structure, and experiments were conducted to study its thermal performance. A total thermal resistance of less than 0.1 K/W was demonstrated for both counter flow and parallel flow configurations. The effects of flow direction and interlayer flow rate ratio were investigated. It was found that for the low flow rate range the parallel flow arrangement results in a better overall thermal performance than the counter flow arrangement; whereas, for the large flow rate range, the total thermal resistances for both the counter flow and parallel flow configurations are indistinguishable. On the other hand, the counter flow arrangement provides better temperature uniformity for the entire flow rate range tested. The effects of localized heating on the overall thermal performance were examined by selectively applying electrical power to the heaters. Numerical simulations were conducted to study the conjugate heat transfer inside the stacked microchannels. Negative heat flux conditions were found near the outlets of the microchannels for the counter flow arrangement. This is particularly evident for small flow rates. The numerical results clearly explain why the total thermal resistance for counter flow arrangement is larger than that for the parallel flow at low flow rates. In addition, laminar flow inside the microchannels were characterized using Micro-PIV techniques. Microchannels of different width were fabricated in silicon, the smallest channel measuring 34 mm in width. Measurements were conducted at various channel depths. Measured velocity profiles at these depths were found to be in reasonable agreement with laminar flow theory. Micro-PIV measurement found that the maximum velocity is shifted significantly towards the top of the microchannels due to the sidewall slope, a common issue faced with DRIE etching. Numerical simulations were conducted to investigate the effects of the sidewall slope on the flow and heat transfer. The results show that the effects of large sidewall slope on heat transfer are significant; whereas, the effects on pressure drop are not as pronounced.