The aim of this project is to design and build an industrialized microprocessor system capable of testing the limits and capabilities of microprocessors in the industrial process control world. The system must be capable of operating in a data logging or control or supervisory capacity. The system consists of a ruggerdized, electrically isolated unit, designed on a "black box" principle, with minimum operator controls. It is housed in a sealed crate with internal access via rows of input and output plugs and connecters. The system has been designed on a modular basis in order to simplify expansion. It can be operated as a small dedicated controller or expanded by the addition of memory and/or industrial I/O modules to its full capacity. The system is based on an INTEL 8080 microprocessor. The industrial interface consists of electrically isolated analog and digital input and output modules which can be selected under program control. There are also up to 64 asynchronous priority encoded alarm channels that can interrupt the control sequence at any time should an alarm condition arise. For debugging hardware and software a plug-on front panel unit is provided.

The dynamic performance of control systems can be improved by incorporating carefully designed compensators. Historically, these compensators have been implemented with analog hardware. However, digitally based compensator designs offer far superior advantages; such as no aging, repeatability, etc. The major reason for rejecting the digital approach to compensator design has been cost. With the introduction of the INTEL 2920 4-input, 8-output, real-time signal processing chip (with AD and DA on-board), cost is no longer a barrier. In this research paper, the complete software-hardware 2920 design cycle required to implement a lead-lag control system compensator is illustrated.

A microprocessor based bus protection scheme has been proposed for a single bus system which employs a new technique to overcome the problem of current transformer saturation. The protection scheme uses a combination of the percentage differential current principle and the phase comparison principle. A sampling rate of 1440 Hz is used. Existing algorithms for a saturation detector are reviewed and a new saturation detector has been developed. This new saturation detector employs the slope difference of the secondary current to determine the CT state. It has a high sensitivity and can reveal early (one-eighth cycle) saturation. With the incorporation of this new saturation detector, the bus relay can make a correct decision for either an internal or an external fault in the presence of current transformer saturation in a half cycle in most cases. The bus protection scheme has been coded in Fortran and tested against data produced from EMTP. The simulated results from eight sets of data are presented in this thesis. All cases show that the bus protection scheme works correctly. The algorithm for the new saturation detector will be implemented using a 32-bit microprocessor by Mr. Paul A. Dolloff. / Master of Science

Vita. / Digitized by Kansas Correctional Industries

No description available.

No description available.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

In microprocessors, achieving an efficient utilization of the execution units is a key factor in improving performance. However, maintaining an uninterrupted flow of instructions is a challenge due to the data and control dependencies between instructions of a program. Modern microprocessors employ aggressive optimizations trying to keep their execution units busy without violating inter-instruction dependencies. Such complex optimizations may cause subtle implementation flaws that can be hard to detect using conventional simulation-based verification techniques. Formal verification is known for its ability to discover design flaws that may go undetected using conventional verification techniques. However, with formal verification come two major challenges. First, the correctness of the implementation needs to be defined formally. Second, formal verification is often hard to apply at the scale of realistic implementations. In this thesis, we present a formal verification strategy to guarantee that a microprocessor implementation preserves both data and control dependencies among instructions. Throughout our strategy, we address the two major challenges associated with formal verification: correctness and scalability. We address the correctness challenge by specifying our correctness in the context of generic pipelines. Unlike conventional pipeline hazard rules, we make no distinction between the data and control aspects. Instead, we describe the relationship between a producer instruction and a consumer instruction in a way such that both instructions can speculatively read their source operands, speculatively write their results, and go out of their program order during execution. In addition to supporting branch and value prediction, our correctness criteria allow the implementation to discard (squash) or replay instructions while being executed. We address the scalability challenge in three ways: abstraction, decomposition, and induction. First, we state our inter-instruction dependency correctness criteria in terms of read and write operations without making reference to data values. Consequently, our correctness criteria can be verified for implementations with abstract datapaths. Second, we decompose our correctness criteria into a set of smaller obligations that are easier to verify. All these obligations can be expressed as properties within the Syntactically-Safe fragment of Linear Temporal Logic (SSLTL). Third, we introduce a technique to verify SSLTL properties by induction, and prove its soundness and completeness. To demonstrate our overall strategy, we verified a term-level model of an out-of-order speculative processor. The processor model implements register renaming using a P6-style reorder buffer and branch prediction with a hybrid (discard-replay) recovery mechanism. The verification obligations (expressed in SSLTL) are checked using a tool implementing our inductive technique. Our tool, named Tahrir, is built on top of a generic interface to SMT solvers and can be generally used for verifying SSLTL properties about infinite-state systems.

Thesis (M.S. in Computer Science and M.S. in Electrical Engineering)--Naval Postgraduate School, March 2004. / Thesis advisor(s): Su Wen, Jon Butler. Includes bibliographical references (p. 53-54). Also available online.

Title from PDF of title page (University of Missouri--Columbia, viewed on Feb 18, 2010). The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Thesis advisor: Dr. Harry Tyrer. Includes bibliographical references.