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The continuous improvement in the speed of digital components in conjunction with reduction of size has brought about a revolutionary age of microprocessors. Mathematical functions, which at one time could only be implemented by complex analog circuitry, can now be easily implemented via microprocessors and high density digital components. Principles of random number generation must be understood in order to implement pseudo-random algorithms in a digital random frequency generator (DRFG) design. Chapter 1 is a discussion of several types of random number algorithms which have been used in the past and outlines the deficiencies and advantages associated with each individual algorithm. In particular, problems such a cycling and maximum period deficiency are discussed. The discussions in Chapter 1 lead to the selection of a random number algorithm which can be used in a DRFG design. There are other characteristics which should be observed in the evaluation of acceptable random number algorithms. In Chapter 2 three tests are described which can be applied in order to test the algorithm for the well-known uniformity and independence criteria. These tests are implemented in a Fortran program which is used to evaluated the algorithm selected in Chapter 1. The random number generator evaluation program (RNGEP) listing is presented in Appendix B. The results of the tests applied to the DRFG random number algorithm are presented in Appendix C.

Microprocessor-Based Closed-Loop Motor Control. A dedicated microprocessor control system was built from chip level using the Motorola M6800 family. The system has a keyboard and the interfaces for four LED displays, a phototransistor and a digital-to-analog converter. The system accepts key input in RPM and drives the motor at the input RPM with display of the real RPM updated approximately every second.

The purpose of this investigation is to research the utility of a standardized generic microprocessor assembly language. More precisely, use of a generic language implementation on a given microprocessor and its effect on programmer productivity will be investigated. Programmer productivity will be scored in terms of an inverse function of the time taken to complete a programming task correctly. Shorter times imply better programmer productivity and longer times imply the opposite

Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement and populate the iLORE data model using data harvested from publicly available sources. Finally, we demonstrate the validity and utility of our iLORE implementation through an analysis of the characteristics and lineage of commercial microprocessors. We encourage the research community to interact with our data and visualizations at csgenome.org. / Master of Science / Researchers, benchmarking organizations, and hardware manufacturers maintain repositories of computer component and performance information. However, this data is split across many isolated sources and is stored in a form that is not conducive to analysis. A centralized repository of said data would arm stakeholders across industry and academia with a tool to more quantitatively understand the history of computing. We propose iLORE, a data model designed to represent intricate relationships between computer system benchmarks and computer components. We detail the methods we used to implement and populate the iLORE data model using data harvested from publicly available sources. Finally, we demonstrate the validity and utility of our iLORE implementation through an analysis of the characteristics and lineage of commercial microprocessors. We encourage the research community to interact with our data and visualizations at csgenome.org.

Procedures for designing and writing a CPU self-test program are developed for microprocessors in general. Specific examples of these procedures are then provided for both a simple example processor and for the Intel 8080; fault coverage statistics are provided for the 8080 test. The self-test methodology overlaps the tests for different elements within the CPU in order to attain a very quick test suitable for periodic background testing. Generalized fault classes are defined for the CPU and methods for sensitizing and detecting these faults are detailed. General procedures and hardware requirements for self-testing the entire microcomputer system within its operating environment are discussed. Fault simulation techniques are also discussed; simulation provides feedback on the effectiveness of a self-test and allows the test to be improved for better coverage and faster execution. / Master of Science

Power optimization becomes more and more important due to the design cost and reliability. Sometimes high power consumption means expensive package cost and low reliability. The first step in optimizing power consumption is determining where power is consumed within a processor. While system-level code tracing and bit transition calculation are not enough to estimate the power distribution, transistor-level HSPICE simulation to model a microprocessor is too complex and time-consuming. In our research, a VHDL model with enhanced signal tracing function will be developed based on the existing VHDL behavior model. The power consumption of superscalar microprocessor in terms of switching activity and capacitance will be carefully studied. Two factors served as the basis for study: accessibility and importance for power calculations. A brief examination of the datapath suggests that the register file, the instruction cache and data cache are some of the major contributors to power usage. It was therefore decided to track the input and output bit transitions to these modules. These transitions are counted along with the number of accesses to each of the modules. In order to gather all of this data, the original VHDL model simulator has been enhanced. As instructions pass through the CPU, additional code is required to track and record the necessary information. For each individual instruction in the ISA, various information is recorded based on the elements in the processor that the instruction affects. For instance, if the simulator is about to execute a load instruction, the instruction uses the programmer counter, the instruction bus, data bus, the address bus, the ALU (adder) and the register file. The information being recorded for each of these elements must be updated to reflect the execution of that particular load instruction. Also, the inside circuit of each module, i.e. register file, instruction cache and data cache and the 6-transistor memory cell layout considering the 0.25��m CMOS technology will be studied in order to extract the capacitance. We do not need very accurate, absolute power estimation, therefore, we will try to keep the model simple. / Graduation date: 2000

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Call number: LD2668 .T4 1984 D84 / Master of Science