During the last two decades, the performance of CPU has been developed much faster than that of memory. In order to reduce the performance gap between CPU and memory, cache memories should have been used between CPU and memory. In general, cache memory is a small and fast buffer to reduce memory access time by saving data in advance before CPU uses. There are two types of cache memory: instruction cache and data cache. In addition, there can be multi-levels (Level 1, 2, ?etc) in memory hierarchy (memory and cache memories) for system purpose: the level 1 (on-chip) cache is the closest one to CPU and it affects system performance directly. In this study, we evaluated two factors in designing an efficient Level 1 data cache. Those factors are: distance between two data in an array and multi xor mapping functions in a bank. We designed a data cache called SLDC (Store/Load Dependent Cache, Two-way) to implement the first factor. This cache uses the distance between two data addresses of data-transfer instructions (load and store). It groups close data into the same group and places into the same bank. The other cache we designed for the second factor is called Multi-XOR (MXOR). The MXOR splits the cache virtually into several zones (2 to 6 areas); a different xor mapping function per area is used to index data (for better cache utilization). In this study, we used the SimpleScalar simulation program to implement data cache with SPEC2000FP benchmark programs. Based on the experiment results, we recommended considering those factors in designing an efficient cache memory since SLDC and MXOR show some improvement (5-to-10%) compared to a conventional cache memory (two-way set-associative).

Miss Rate Curves (MRCs) for main memory have been proposed as a representation of memory utilization for use in a range of optimizations in the area of memory man- agement. Various techniques exist for their creation; however, all real-world methods of MRC generation must make trade-offs between overhead and accuracy. Proposals for new hardware techniques exist, but have yet to be implemented in actual hardware. We pro- pose the use of the Intel PEBS (Precise Event-Based Sampling) performance monitoring capability for the task of MRC generation on existing commodity hardware. We use PEBS to generate MRCs and compare them against MRCs generated through instrumentation, finding the PEBS MRCs to be good, but imperfect approximations, while keeping average PEBS overheads below 5%. We were unable to show that PEBS is better or worse than existing techniques, but believe we have succeeded in showing the promise of the use of general purpose performance monitoring hardware for this task and in motivating future research and development in this area.

Miss Rate Curves (MRCs) for main memory have been proposed as a representation of memory utilization for use in a range of optimizations in the area of memory man- agement. Various techniques exist for their creation; however, all real-world methods of MRC generation must make trade-offs between overhead and accuracy. Proposals for new hardware techniques exist, but have yet to be implemented in actual hardware. We pro- pose the use of the Intel PEBS (Precise Event-Based Sampling) performance monitoring capability for the task of MRC generation on existing commodity hardware. We use PEBS to generate MRCs and compare them against MRCs generated through instrumentation, finding the PEBS MRCs to be good, but imperfect approximations, while keeping average PEBS overheads below 5%. We were unable to show that PEBS is better or worse than existing techniques, but believe we have succeeded in showing the promise of the use of general purpose performance monitoring hardware for this task and in motivating future research and development in this area.

DNA microarrays are a relatively new technology for assessing the expression levels of thousands of genes simultaneously. Researchers hope to find genes that are differentially expressed by hybridizing cDNA from known treatment sources with various genes spotted on the microarrays. The large number of tests involved in analyzing microarrays has raised new questions in multiple testing. Several approaches for identifying differentially expressed genes have been proposed. This paper considers two: (1) a mixed models approach, and (2) the Signiffcance Analysis of Microarrays.