The proliferation of products from the consumer electronics industry (especially the communications market) has led to increasing consumer demand for cheaper, smaller form factor, efficient and low power consumption products with high computation power. This growing demand for cheaper and more efficient products has made it more desirable for Integrated Circuit (IC) manufacturers to integrate both analogue and digital circuits on the same silicon substrate in order to realise high performance mixed-signal IC's at cost effective prices. The concomitant technology advancements in the IC manufacturing process, especially in the Complementary Metal Oxide Semiconductor (CMOS) process and improvements made in the capabilities of Computer-Aided Design (CAD) tools is making greater system integration possible. However, one aspect of the process that is the bottleneck of yet further system integration and lower design lead time is test. While the digital sections of mixed-signal IC's are taking microseconds to test using well established digital structural test techniques which exploit efficient Design for Test (DFT) structures, the analogue sections are still being tested using functional test methods and consequently consume several seconds of expensive test time. The work presented in this thesis addresses the test problems associated with the analogue sections of mixed-signal IC's. Specifically, the work was aimed at developing an efficient and unified embedded mixed-signal test system capable of being adopted for both analogue circuit characterisation and production testing of mixed-signal IC's in order to reduce overall test time and cost. In this context, an Analogue Test Response Compaction Technique (ATRCT) has been developed using Delta-Sigma Modulation (AIM). This compaction technique produces a signature for an analogue macro under test, which relates to both the amplitude and frequency of the analogue output response. Fault simulation results relating to a two-stage CMOS operational amplifier and continuous-time state variable filter have shown that fault-coverage of greater than 80% is attainable when the ATRCT is employed in a production testing of linear analogue macros. Based on the ATRCT, a hardware efficient Analogue Built-In Selt-Test (ABIST) scheme is proposed. This work has also developed two characterisation techniques suitable for embedded linear analogue macros: 1) An alternative hardware efficient method of measuring the impulse response of linear analogue macros using AIM, which could be conveniently incorporated in an ABIST scheme. Simulation results of the AIM-based impulse response measurement system have shown that the accuracy of the technique is within ±0.5% of the expected impulse responses. 2) An analogue fault detection routine that uses AIM and correlation techniques to detect analogue amplitude and frequency faults within linear analogue macros. Combining the proposed AIM-based impulse response measurement technique with the proposed ABIST scheme or analogue fault detection routine will enable an efficient and unified embedded mixed-signal test system to be designed.

Test strategies were developed to reduce the overall production testing cost of high-performance data converters. A static linearity testing methodology, aimed at reducing the test time of A/D converters, was developed. The architectural information of A/D converters was used, and specific codes were measured. To test a high-performance A/D converters using low-performance and low-cost test equipment a dynamic testing methodology was developed. This involved post processing of measurement data. The effect of ground bounce on accuracy of specification measurement was analyzed, and a test strategy to estimate the A/D converter specifications more accurately in presence of ground bounce noise was developed. The proposed test strategies were simulated using behavioral modeling techniques and were implemented on commercially available A/D converter devices. The hardware experiments validated the proposed test strategies. The test cost analysis was done. It suggest that a significant reduction in cost can be obtained by using the proposed test methodologies for data converter production testing.

Abstract This thesis studies the methods to test mixed-signal devices and circuits on board and system level with embedded test instrumentation. The study is divided in three continuous sections, development of embedded test methods for discrete components, integration of test instruments on board level and development of test and health monitoring strategy for large scale system. The developed embedded test methods for mixed signal circuitry on board level are based on the standard for mixed signal test bus IEEE 1149.4. The standardized embedded test infrastructure is utilized for testing discrete components with emphasis on testing active components as diodes and transistors. The developed embedded tests are evaluated with PCOLA/SOQ method for manufacturing testing and also the usability of the tests is discussed. A solution for embedded mixed-signal test controller is presented with discussion of test communication and the possibilities of implementing embedded test control. The target in the development of the test control is to enable launch mixed signal tests on device remotely. The test controller is IEEE 1149.4 compatible and can generate and measure analog test signals while controlling boundary-scan enabled devices. The final section of the thesis focuses on an embedded test solution for aerospace bus system (MIL-STD-1553). Current solutions are based on testing the bus system during maintenance on ground. The developed test and monitoring method allows on-line monitoring of the bus to detect and locate possible defects which only occur during use of the aeroplane. / Tiivistelmä Väitöstyössä tutkittiin sekasignaalilaitteiden ja -piirien testausmenetelmiä levy- ja järjestelmätasolla hyödyntäen sulautettuja testilaitteita. Työ jakaantuu kolmeen osaan; sulautettujen testausmenetelmien kehitys diskreeteille komponenteille, testi-instrumenttien integrointi piirilevytasolle sekä testaus- ja kunnonmonitorointimenetelmän kehitys laajemmalle järjestelmälle. Sulautettujen testimenetelmien kehitys sekasignaalipiireille piirilevytasolla perustuu sekasignaalitestiväylän standardiin IEEE 1149.4. Standardoitua sulautettua testi-infrastruktuuria käytettiin diskreettien komponenttien testaukseen painottuen aktiivikomponentteihin, kuten diodeihin ja transistoreihin. Kehitetyt sulautetut testit on arvioitu PCOLA/SOQ menetelmällä, jota hyödynnetään tuotantotestauksen testikattavuuden arvioinnissa. Lisäksi testimenetelmien käytettävyyttä arvioitiin. Sulautettu sekasignaalilaitteiden testikontrollerin tavoite on käynnistää ja suorittaa sekasignaalitestejä laitteessa etäältä. Kehitetty testikontrolleri on IEEE 1149.4 yhteensopiva ja voi generoida ja mitata analogista testisignaalia sekä samanaikaisesti ohjata testiväylää. Lisäksi etätestauksen mahdollistavasta testikommunikaatiomenetelmiä arvioitiin kuten myös erilaisia toteutustasoja sulautetuille testimenetelmille. Laajemman järjestelmän kehityksessä tutkittiin sulautettua testausratkaisua lentokoneen väyläjärjestelmälle, joka perustuu standardiin MIL-STD-1553B. Nykyiset menetelmät perustuvat väyläjärjestelmän testaukseen huollon yhteydessä, mutta osa virheistä ilmenee vain käytön aikana. Kehitetty testaus- ja monitorointimenetelmä mahdollistaa käytönaikaisen jatkuvan virheiden monitoroinnin sekä niiden paikantamisen lennon aikana.