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O trabalho usa a síntese do leiaute através do ASTRAN em circuitos que foram otimizados através da técnica de SCCG (Static CMOS Complex Gates) visando alcançar reduções em número de transistores. A metodologia apresentada permite a flexibilidade de utilizar células de quaisquer tamanho ou redes de transistores nos circuito otimizados. O trabalho compara estes circuitos otimizados pela método do ASTRAN e circuitos utilizando a metodologia standard cell. O fluxo de síntese é composto pelas etapas de otimização da netlist, verificação/extração e caracterização da células. O trabalho adaptou as tecnologias de fabricação CMOS de 600nm e 180nm para a ferramenta ASTRAN a partir das informações dos design kits das bibliotecas stantard cell XC06 e XC018 da XFAB. A síntese do leiaute das células complexas geradas é realizada pela ferramenta ASTRAN. Os experimentos foram realizados nas tecnologias de 180nm e 600nm para um conjunto de circuitos de bechmarks do ITC’99. As comparações foram realizadas entre a netlist otimizada e duas netlists geradas para cada biblioteca da XFAB. Uma netlist abrange todas as células da biblioteca e a outra tem uma restrição de células que são consideradas complexas (somadores, multiplexadores, XOR/XNOR, AOI e OAI). A netlist com restrições foi elaborada com a motivação de verificar se uma netlist com células complexas geradas exclusivamente para o circuito alvo se tornaria mais benéfico em termos de redução do número de transistores. Os resultados para 180nm apresentaram reduções nos melhores casos em número de transistores com até 15%, em potência dinâmica com até 24% e em potência de leakage com até 22%. Os resultados para 600nm apresentaram reduções nos melhores casos em número de transistores com até 17%, em área com até 14%, em potência dinâmica com até 22%, em potência de leakage com até 29%. Os experimentos mostraram que é possível alcançar reduções em número de transistores ao combinar o uso do ASTRAN com a técnica de otimização pelo uso de SCCG. / The work uses the synthesis of the layout through ASTRAN in circuits that have been optimized through the SCCG technique (Static CMOS Complex Gates) in order to achieve reductions in the number of transistors. The presented methodology allows the flexibility of using cells of any size or transistor networks in the optimized circuits. The work compares these circuits optimized by the ASTRAN method and circuits using the standard cell methodology. The synthesis flow is composed by the netlist optimization, verification / extraction and cell characterization steps. The work adapted 600nm and 180nm CMOS fabrication technologies for the ASTRAN tool from the design information of the XFAB standard cell XC06 and XC018 libraries. The synthesis of the complex cells generated is performed by the ASTRAN tool. The experiments were performed on the 180nm and 600nm technologies for a set of ITC'99 bechmarks circuits. Comparisons were made between the optimized netlist and two netlists generated for each XFAB library. A netlist covers all cells in the library and the other netlist has a restriction of cells that are considered complex (adders, multiplexers, XOR / XNOR, AOI, and OAI). The netlist with restrictions was designed with the motivation to check if a netlist with complex cells generated exclusively for the target circuit would become more beneficial in terms of reducing the number of transistors. The results for 180nm showed reductions in the best cases in the number of transistors with up to 15%, in dynamic power up to 24% and in leakage power with up to 22%. The results for 600nm showed reductions in the best cases in the number of transistors with up to 17%, in an area up to 14%, in dynamic power with up to 22%, in leakage power with up to 29%. The experiments showed that it is possible to achieve reductions in the number of transistors by combining the use of ASTRAN with the optimization technique using SCCG.

<p>The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. The sooner you find a bug in the design, the shorter the turnaround time becomes, and thereby both time and money will be saved.</p><p>There are a couple of tools in the market that performs static HDL analysis and they vary in both price and functionality. In this project mainly Atrenta Spyglass was evaluated but similar tools were also evaluated for comparison purpose.</p><p>The purpose of this master thesis was to evaluate the need of implementing a rule checking tool in the design flow at the Digital ASIC department PDU Base Station development in Kista, who also was the commissioner for this project. Based on the findings in this project it is recommended that a static rule checking tool is introduced in the design flow at the ASIC department. However, in order to determine which of the different tools the following pointers should be regarded:</p><p>• If the tool is only going to be used as for lint checks (elementary structure and code checks) on RTL, then the implementation of Mentors Design Checker is advised.</p><p>• If the tool is going to be used for more sophisticated structural checks, clock tree/reset tree propagation, code checks, basic constraints checks, basic Clock Domain Crossings (CDC) checks, then Synopsys LEDA is advised.</p><p>• If the tool is going to be used as for advanced structural checks, extensive clock tree/reset tree propagation, code checks, constraints checks, functional Design For Test (DFT) checks (as testmode signal propagation) and functional CDC checks on RTL as well as on netlist level, then Atrenta Spyglass is advised.</p><p>The areas regarding checks that could be of interest for Ericsson is believed to be regular lint checks for RTL (naming, code and basic structure), clock/reset tree propagation (netlist and RTL), constraints and functional DFT checks (netlist and RTL).</p>

The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. The sooner you find a bug in the design, the shorter the turnaround time becomes, and thereby both time and money will be saved. There are a couple of tools in the market that performs static HDL analysis and they vary in both price and functionality. In this project mainly Atrenta Spyglass was evaluated but similar tools were also evaluated for comparison purpose. The purpose of this master thesis was to evaluate the need of implementing a rule checking tool in the design flow at the Digital ASIC department PDU Base Station development in Kista, who also was the commissioner for this project. Based on the findings in this project it is recommended that a static rule checking tool is introduced in the design flow at the ASIC department. However, in order to determine which of the different tools the following pointers should be regarded: • If the tool is only going to be used as for lint checks (elementary structure and code checks) on RTL, then the implementation of Mentors Design Checker is advised. • If the tool is going to be used for more sophisticated structural checks, clock tree/reset tree propagation, code checks, basic constraints checks, basic Clock Domain Crossings (CDC) checks, then Synopsys LEDA is advised. • If the tool is going to be used as for advanced structural checks, extensive clock tree/reset tree propagation, code checks, constraints checks, functional Design For Test (DFT) checks (as testmode signal propagation) and functional CDC checks on RTL as well as on netlist level, then Atrenta Spyglass is advised. The areas regarding checks that could be of interest for Ericsson is believed to be regular lint checks for RTL (naming, code and basic structure), clock/reset tree propagation (netlist and RTL), constraints and functional DFT checks (netlist and RTL).

The diploma thesis deals with creating of electronic schematics in editor using web interface. The editor generates electrical circuit text file according to Spice netlist specification. The program has been created in Java and takes an advantage of object oriented programming language. The editor is a part of a web page and is executable as an applet. The diploma thesis describes a programming language selection, program layout and implementation. Thesis contains programming code examples, window illustration and component drawings. Depth-first search algorithm has been used for nodes number assignment. An OrCAD PSpice reference guide was used for netlist.

This project deals with the computer analysis of circuits with external switching. At the first of all there is a description of the creation of the entry of the program CIRNAM – description of the circuit, modified netlist. The work also discusses the theory used for solutions of analysed circuits. In the other part there is a description of the program CIRNAM in full details. In the next parts of this project there is the illustration of work in the program, which is shown on the examples with short discussion of output options – he rendering of the frequency characteristics in the program CIRNAM or the export of calculated data to MATLAB. There are also described the source code of CIRNAM for the initial orientation of the programmer, which would extend the possibilities of this program.

No description available.

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This master´s thesis on theme Modeling of the unconventional functional blocks in Pspice deals with the design procedures of electronic elements models and should to help with their create. At the beginning the thesis theoretically describes how the models are created and what possibilities for modeling the program Pspice offers. There are drawn near the individual levels of model and their properties. The second main part of thesis shows practically step by step the design procedures of models of the operational amplifier, current and voltage conveyors, OTA, CDTA, immittance inverter and converter and logarithmic amplifier. There are created the models up to 4.th level, the ideal, resistive, frequency dependent and nonlinear. The basic transmission properties, input and output impedance are modeled this way. The created models with sufficient accuracy correspond to the parameters of the commercial elements. This thesis such shows the possibilities of the program for finding of values for model components like stepping or Optimizer tool.

While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted