Tang Ko Cheung, Simon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 89-91). / Abstracts in English and Chinese. / Chapter 1 --- Theory of Optimal Normal Bases --- p.3 / Chapter 1.1 --- Introduction --- p.3 / Chapter 1.2 --- The minimum number of terms --- p.6 / Chapter 1.3 --- Constructions for optimal normal bases --- p.7 / Chapter 1.4 --- Existence of optimal normal bases --- p.10 / Chapter 2 --- Implementing Multiplication in GF(2m) --- p.13 / Chapter 2.1 --- Defining the Galois fields GF(2m) --- p.13 / Chapter 2.2 --- Adding and squaring normal basis numbers in GF(2m) --- p.14 / Chapter 2.3 --- Multiplication formula --- p.15 / Chapter 2.4 --- Construction of Lambda table for Type I ONB in GF(2m) --- p.16 / Chapter 2.5 --- Constructing Lambda table for Type II ONB in GF(2m) --- p.21 / Chapter 2.5.1 --- Equations of the Lambda matrix --- p.21 / Chapter 2.5.2 --- An example of Type IIa ONB --- p.23 / Chapter 2.5.3 --- An example of Type IIb ONB --- p.24 / Chapter 2.5.4 --- Creating the Lambda vectors for Type II ONB --- p.26 / Chapter 2.6 --- Multiplication in practice --- p.28 / Chapter 3 --- Inversion over optimal normal basis --- p.33 / Chapter 3.1 --- A straightforward method --- p.33 / Chapter 3.2 --- High-speed inversion for optimal normal basis --- p.34 / Chapter 3.2.1 --- Using the almost inverse algorithm --- p.34 / Chapter 3.2.2 --- "Faster inversion, preliminary subroutines" --- p.37 / Chapter 3.2.3 --- "Faster inversion, the code" --- p.41 / Chapter 4 --- Elliptic Curve Cryptography over GF(2m) --- p.49 / Chapter 4.1 --- Mathematics of elliptic curves --- p.49 / Chapter 4.2 --- Elliptic Curve Cryptography --- p.52 / Chapter 4.3 --- Elliptic curve discrete log problem --- p.56 / Chapter 4.4 --- Finding good and secure curves --- p.58 / Chapter 4.4.1 --- Avoiding weak curves --- p.58 / Chapter 4.4.2 --- Finding curves of appropriate order --- p.59 / Chapter 5 --- The performance of 17x bit Elliptic Curve Scalar Multiplication --- p.63 / Chapter 5.1 --- Choosing finite fields --- p.63 / Chapter 5.2 --- 17x bit test vectors for onb --- p.65 / Chapter 5.3 --- Testing methodology and sample runs --- p.68 / Chapter 5.4 --- Proposing an elliptic curve discrete log problem for an 178bit curve --- p.72 / Chapter 5.5 --- Results and further explorations --- p.74 / Chapter 6 --- On matrix RSA --- p.77 / Chapter 6.1 --- Introduction --- p.77 / Chapter 6.2 --- 2 by 2 matrix RSA scheme 1 --- p.80 / Chapter 6.3 --- Theorems on matrix powers --- p.80 / Chapter 6.4 --- 2 by 2 matrix RSA scheme 2 --- p.83 / Chapter 6.5 --- 2 by 2 matrix RSA scheme 3 --- p.84 / Chapter 6.6 --- An example and conclusion --- p.85 / Bibliography --- p.91

Thesis (Ph. D.)--Oregon State University, 2003. / Typescript (photocopy). Includes bibliographical references (leaves 43-46). Also available on the World Wide Web.

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<p>This thesis investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer. </p><p>The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can. </p><p>Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.</p>

Let p be a prime and q = pk. The polynomial gn,q isin Fp[x] defined by the functional equation Sigmaa isin Fq (x+a)n = gn,q(xq- x) gives rise to many permutation polynomials over finite fields. We are interested in triples (n,e;q) for which gn,q is a permutation polynomial of Fqe. In Chapters 2, 3, and 4 of this dissertation, we present many new families of permutation polynomials in the form of gn,q. The permutation behavior of gn,q is becoming increasingly more interesting and challenging. As we further explore the permutation behavior of gn,q, there is a clear indication that gn,q is a plenteous source of permutation polynomials. We also describe a piecewise construction of permutation polynomials over a finite field Fq which uses a subgroup of Fq*, a “selection” function, and several “case” functions. Chapter 5 of this dissertation is devoted to this piecewise construction which generalizes several recently discovered families of permutation polynomials.

This thesis investigates architectures for multiplying elements in Galois rings of the size 4^m, where m is an integer. The main question is whether known architectures for multiplying in Galois fields can be used for Galois rings also, with small modifications, and the answer to that question is that they can. Different representations for elements in Galois rings are also explored, and the performance of multipliers for the different representations is investigated.

With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults specially in sensitive and critical applications may cause serious failures and hence should be avoided. On the other hand, some critical applications such as cryptosystems may also be prone to deliberately injected faults by malicious attackers. Some of these faults can produce erroneous results that can reveal some important secret information of the cryptosystems. Furthermore, yield factor improvement is always an important issue in VLSI design and fabrication processes. Digital systems such as cryptosystems and digital signal processors usually contain finite field operations. Therefore, error detection and correction of such operations have become an important issue recently. In most of the work reported so far, error detection and correction are applied using redundancies in space (hardware), time, and/or information (coding theory). In this work, schemes based on these redundancies are presented to detect errors in important finite field arithmetic operations resulting from hardware faults. Finite fields are used in a number of practical cryptosystems and channel encoders/decoders. The schemes presented here can detect errors in arithmetic operations of finite fields represented in different bases, including polynomial, dual and/or normal basis, and implemented in various architectures, including bit-serial, bit-parallel and/or systolic arrays.

With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults specially in sensitive and critical applications may cause serious failures and hence should be avoided. On the other hand, some critical applications such as cryptosystems may also be prone to deliberately injected faults by malicious attackers. Some of these faults can produce erroneous results that can reveal some important secret information of the cryptosystems. Furthermore, yield factor improvement is always an important issue in VLSI design and fabrication processes. Digital systems such as cryptosystems and digital signal processors usually contain finite field operations. Therefore, error detection and correction of such operations have become an important issue recently. In most of the work reported so far, error detection and correction are applied using redundancies in space (hardware), time, and/or information (coding theory). In this work, schemes based on these redundancies are presented to detect errors in important finite field arithmetic operations resulting from hardware faults. Finite fields are used in a number of practical cryptosystems and channel encoders/decoders. The schemes presented here can detect errors in arithmetic operations of finite fields represented in different bases, including polynomial, dual and/or normal basis, and implemented in various architectures, including bit-serial, bit-parallel and/or systolic arrays.

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