This report aims to provide a complete specification of an IEEE-754 1985 compliantdesign, as well as a working, synthesizable implementation in Verilog HDL. Thereport is based on a preliminary project, which analyzed the IEEE-754 standardand suggested a set of algorithms suitable for a compact realization.Through traditional methods of both algorithmic analysis and dataanalysis,requirements of functional units are derived, and operations are scheduled.A set of functional simulations assert the correctness of the design, while areaand performance analysis provides information on the speedup gained, versus thehardware cost.Finally, the results obtained are compared to existing implementations, bothhardware and software.