Channel coding plays a vital role in telecommunication. Low-Density Parity- Check (LDPC) codes are linear error-correcting codes. According to the 3rd Generation Partnership Project (3GPP) TS 38.212, LDPC is recommended for the Fifth-generation (5G) New Radio (NR) shared channels due to its high throughput, low latency, low decoding complexity and rate compatibility. LDPC encoding chain has been defined in 3GPP TS 38.212, but some details of LDPC encoding chain are still required to be explored in the MATLAB environment. For example, how to deal with the filler bits for encoding and decoding. However, as the reverse process of LDPC encoding, there is no information on LDPC decoding process for 5G NR shared channels in 3GPP TS 38.212. In this thesis project, LDPC encoding and decoding chains were thoughtfully developed with MATLAB programming based on 3GPP TS 38.212. Several LDPC decoding algorithms were implemented and optimized. The performance of LDPC algorithms was evaluated using block error rate (BLER) v.s. signal to noise ratio (SNR) and CPU time. Results show that the double diagonal structure-based encoding method is an efficient LDPC encoding algorithm for 5G NR. Layered Sum Product Algorithm (LSPA) and Layered Min-Sum Algorithm (LMSA) are more efficient than Sum Product Algorithm (SPA) and Min-Sum Algorithm (MSA). Layered Normalized Min-Sum Algorithm (LNMSA) with proper normalization factor and Layered Offset Min-Sum Algorithm (LOMSA) with good offset factor can optimize LMSA. The performance of LNMSA and LOMSA decoding depends more on code rate than transport block. / Kanalkodning spelar en viktig roll i telekommunikation. Paritetskontrollkoder med låg densitet (LDPC) är linjära felkorrigeringskoder. Enligt tredje generationens partnerskapsprojekt (3GPP) TS 38.212, LDPC rekommenderas för den femte generationens (5G) nya radio (NR) delade kanal på grund av dess höga genomströmning, låga latens, låga avkodningskomplexitet och hastighetskompatibilitet. LDPC kodningskedjan har definierats i 3GPP TS 38.212, men vissa detaljer i LDPC kodningskedjan krävs fortfarande för att utforskas i Matlabmiljön. Till exempel hur man hanterar fyllnadsbitar för kodning och avkodning. Men som den omvända processen för LDPC kodning finns det ingen information om LDPC avkodningsprocessen för 5G NR delade kanaler på 3GPP TS 38.212. I detta avhandlingsprojekt utvecklades LDPC-kodning och avkodningskedjor enligt 3GPP TS 38.212. Flera LDPC-avkodningsalgoritmer implementerades och optimerades. Prestandan för LDPC-algoritmer utvärderades med användning av blockfelshalt (BLER) v.s. signal / brusförhållande (SNR) och CPU-tid. Resultaten visar att den dubbla diagonala strukturbaserade kodningsmetoden är en effektiv LDPC kodningsalgoritm för 5G NR. Layered Sum Product Algorithm (LSPA) och Layered Min-Sum Algorithm (LMSA) är effektivare än Sum Product Algorithm (SPA) och Min-Sum Algorithm (MSA). Layered Normalized Min-Sum Algorithm (LNMSA) med rätt normaliseringsfaktor och Layered Offset Min-Sum Algorithm (LOMSA) med bra offsetfaktor kan optimera LMSA. Prestandan för LNMSA- och LOMSA-avkodning beror mer på kodhastighet än transportblock.

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by the interconnect and the storage requirements. This dissertation presents the decoder architectures for regular and irregular LDPC codes that provide substantial gains over existing academic and commercial implementations. Several structured properties of LDPC codes and decoding algorithms are observed and are used to construct hardware implementation with reduced processing complexity. The proposed architectures utilize an on-the-fly computation paradigm which permits scheduling of the computations in a way that the memory requirements and re-computations are reduced. Using this paradigm, the run-time configurable and multi-rate VLSI architectures for the rate compatible array LDPC codes and irregular block LDPC codes are designed. Rate compatible array codes are considered for DSL applications. Irregular block LDPC codes are proposed for IEEE 802.16e, IEEE 802.11n, and IEEE 802.20. When compared with a recent implementation of an 802.11n LDPC decoder, the proposed decoder reduces the logic complexity by 6.45x and memory complexity by 2x for a given data throughput. When compared to the latest reported multi-rate decoders, this decoder design has an area efficiency of around 5.5x and energy efficiency of 2.6x for a given data throughput. The numbers are normalized for a 180nm CMOS process. Properly designed array codes have low error floors and meet the requirements of magnetic channel and other applications which need several Gbps of data throughput. A high throughput and fixed code architecture for array LDPC codes has been designed. No modification to the code is performed as this can result in high error floors. This parallel decoder architecture has no routing congestion and is scalable for longer block lengths. When compared to the latest fixed code parallel decoders in the literature, this design has an area efficiency of around 36x and an energy efficiency of 3x for a given data throughput. Again, the numbers are normalized for a 180nm CMOS process. In summary, the design and analysis details of the proposed architectures are described in this dissertation. The results from the extensive simulation and VHDL verification on FPGA and ASIC design platforms are also presented.