Thesis (Ph.D.)--University of Western Australia, 2007.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Laskar Joy; Committee Member: Cressler John; Committee Member: Tentzeris Emmanouil

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 100-102). Also available in electronic version.

No description available.

The behavior of the phase-controlled oscillator has been the subject of extensive analysis for many years. However, the vast majority of the literature assumes that the phase comparator, or error detector, of the system produces an output proportional to the sine of the phase difference. In recent years, a few articles have appeared in the literature considering a comparator that produces an output which is proportional to a linear function of the phase difference over a periodic range. This type of phase comparator now makes it plausible to use phase-lock techniques to generate a Fourier series. This paper is concerned with the analysis of the phase-controlled oscillator with the previous mentioned application foremost in mind. To obviate certain mathematical complexities, assumptions were made about the nature of the solution of the equation governing the phase-controlled oscillator. In order to gain insight into the validity of these assumptions, as well as the over-all behavior of the system, a phase-controlled oscillator was designed and constructed. Various measurement techniques were developed to provide both static and dynamic characteristics. / M.S.

High speed serial links are critical components for addressing the growing demand for I/O bandwidth in next-generation computing applications, such as many-core systems, backplane and optical data communications. Due to continued process scaling and circuit innovations, today's CMOS serial link transceivers can achieve tens of Gb/s per pin. However, most of their reported power efficiency improves much slower than the rise of data rate. Therefore, aggregate I/O power is increasing and will exceed the power budget if the trend for more off-chip bandwidth is sustained. In this work, a system level statistical analysis of serial links is first described, and compares the link performance of Non-Return-to-Zero (2-PAM) with higher-order modulation (duobinary) signaling schemes. This method enables fast and accurate BER distribution simulation of serial link transceivers that include channel and circuit imperfections, such as finite pulse rise/fall time, duty cycle variation, and both receiver and transmitter forwarded-clock jitter. Second, in order to address link power efficiency, two test chips have been implemented. The first one describes a quad-lane, 6.4-7.2 Gb/s serial link receiver prototype using a forwarded clock architecture. A novel phase deskew scheme using injection-locked ring oscillators (ILRO) is proposed that achieves greater than one UI of phase shift for multiple clock phases, eliminating phase rotation and interpolation required in conventional architectures. Each receiver, optimized for power efficiency, consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator coupled to a low-voltage swing, global clock distribution. Measurement results show a 6.4-7.2Gb/s data rate with BER < 10⁻¹² across 14 cm of PCB, and an 8Gb/s data rate through 4cm of PCB. Designed in a 1.2V, 90nm CMOS process, the ILRO achieves a wide tuning range from 1.6-2.6GHz. The total area of each receiver is 0.0174mm², resulting in a measured power efficiency of 0.6mW/Gb/s. Improving upon the first test chip, a second test chip for 8Gb/s forwarded clock serial link receivers exploits a low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and deskewing. Further power reduction is achieved by designing most of the receiver circuits in the near-threshold region (0.6V supply), with the exception of only the global clock buffer, test buffers and synthesized digital test circuits at nominal 1V supply. At the architectural level, a 1:10 direct demultiplexing rate is chosen to achieve low supply operation by exploiting high-parallelism. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this test chip, one without and the other with front-end boot-strapped S/Hs. Including the amortized power of global clock distribution, the proposed serial link receivers consume 1.3mW and 2mW respectively at 8Gb/s input data rate, achieving a power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers achieve BER < 10⁻¹² across a 20-cm FR4 PCB channel. / Graduation date: 2012

Leung Lai-Kan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 131-154). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Table of Contents --- p.iv / List of Figures --- p.ix / List of Tables --- p.xv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Overview --- p.1 / Chapter 1.2 --- Objectives --- p.2 / Chapter 1.3 --- Thesis Organization --- p.4 / Chapter Chapter 2 --- Fundamentals of Voltage Controlled Oscillators --- p.6 / Chapter 2.1 --- Definition of Commonly Used Figures of Merit --- p.6 / Chapter 2.1.1 --- Cutoff frequency --- p.6 / Chapter 2.1.2 --- Center Frequency --- p.8 / Chapter 2.1.3 --- Tuning Range --- p.8 / Chapter 2.1.4 --- Tuning Sensitivity --- p.8 / Chapter 2.1.5 --- Output Power --- p.8 / Chapter 2.1.6 --- Power Consumption --- p.9 / Chapter 2.1.7 --- Supply Pulling --- p.9 / Chapter 2.2 --- Phase Noise --- p.9 / Chapter 2.2.1 --- Definition of Phase Noise --- p.9 / Chapter 2.2.2 --- Phase Noise Specification --- p.11 / Chapter 2.2.3 --- Leeson's formula --- p.12 / Chapter 2.2.4 --- Models developed by J. Cranincks and M. Steyaert10 --- p.13 / Chapter 2.2.5 --- Linear Time-Variant Phase Noise Model --- p.13 / Chapter 2.3 --- Building Blocks of Voltage Controlled Oscillators --- p.17 / Chapter 2.3.1 --- FETs --- p.17 / Chapter 2.3.2 --- Varactor --- p.18 / Chapter 2.3.3 --- Spiral Inductor --- p.21 / Chapter 2.3.4 --- Modeling of the Spiral Inductor --- p.24 / Chapter 2.3.5 --- Analysis and Simulation --- p.26 / Chapter Chapter 3 --- Digital Controlled Oscillator --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- General Principle of Oscillation --- p.28 / Chapter 3.3 --- Different Oscillator Architectures --- p.30 / Chapter 3.3.1 --- Single-ended Ring Oscillator --- p.30 / Chapter 3.3.2 --- Differential Ring Oscillator --- p.32 / Chapter 3.3.3 --- CMOS Injection-locked Oscillator --- p.33 / Chapter 3.4 --- Basic Principle of the Injection-locked Oscillator --- p.34 / Chapter 3.5 --- Digital Controlled Oscillator --- p.36 / Chapter 3.5.1 --- R-2R Digital-to-Analog Converter --- p.37 / Chapter 3.6 --- Injection Locking --- p.42 / Chapter 3.6.1 --- Synchronization Model of the Injection Locked Oscillator --- p.42 / Chapter 3.7 --- Simulation Results --- p.44 / Chapter 3.7.1 --- Frequency Tuning Characteristics --- p.44 / Chapter 3.7.2 --- Phase Noise Performance --- p.47 / Chapter 3.7.3 --- Locking Characteristics --- p.48 / Chapter 3.7.4 --- Sensitivity to Supply Voltage and Temperature --- p.48 / Chapter 3.8 --- Conclusion --- p.49 / Chapter Chapter 4 --- CMOS LC Voltage Controlled Oscillator --- p.51 / Chapter 4.1 --- Introduction --- p.51 / Chapter 4.2 --- LC Oscillator --- p.52 / Chapter 4.3 --- Circuit Design --- p.54 / Chapter 4.3.1 --- Oscillation Frequency --- p.55 / Chapter 4.3.2 --- Oscillation Amplitude --- p.58 / Chapter 4.3.3 --- Transistor Sizing --- p.59 / Chapter 4.3.4 --- Power Consumption --- p.62 / Chapter 4.3.5 --- Tuning Range --- p.62 / Chapter 4.3.6 --- Phase Noise Analysis --- p.63 / Chapter 4.4 --- Conclusion --- p.70 / Chapter Chapter 5 --- LC Quadrature Voltage Controlled Oscillator --- p.71 / Chapter 5.1 --- Introduction --- p.71 / Chapter 5.2 --- Conventional CMOS Quadrature LC Voltage Controlled Oscillator --- p.73 / Chapter 5.3 --- Operational Principle of the CMOS Quadrature LC Voltage Controlled Oscillator --- p.74 / Chapter 5.3.1 --- General Explanation --- p.74 / Chapter 5.3.2 --- Mathematical Analysis --- p.75 / Chapter 5.3.3 --- Drawback of the Conventional CMOS LC Quadrature VCO --- p.77 / Chapter 5.4 --- Novel CMOS Low Noise Quadrature Voltage Controlled Oscillator --- p.78 / Chapter 5.4.1 --- Equivalent Output Noise due to the Coupling Transistor --- p.80 / Chapter 5.4.2 --- Linear Time Varying Model for the Analysis of Total Phase Noise --- p.83 / Chapter 5.4.3 --- Tuning Range --- p.94 / Chapter 5.4.4 --- Start-up Condition --- p.95 / Chapter 5.4.5 --- Power Consumption --- p.97 / Chapter 5.5 --- New Tuning Mechanism of the Proposed LC Quadrature VCO --- p.98 / Chapter 5.6 --- Modified Version of the Proposed LC Quadrature Voltage Controlled Oscillator --- p.105 / Chapter 5.7 --- Conclusion --- p.108 / Chapter Chapter 6 --- Layout Consideration --- p.109 / Chapter 6.1 --- Substrate Contacts --- p.109 / Chapter 6.2 --- Guard Rings --- p.110 / Chapter 6.3 --- Thermal Noise of the Gate Interconnect --- p.111 / Chapter 6.4 --- Use of Different Layers of Metal for Interconnection --- p.112 / Chapter 6.5 --- Slicing of Transistors --- p.113 / Chapter 6.6 --- Width of Interconnecting Wires and Numbers of Vias --- p.114 / Chapter 6.7 --- Matching of Devices --- p.114 / Chapter 6.8 --- Die Micrographs of the Prototypes of the Oscillators --- p.115 / Chapter Chapter 7 --- Experimental Results --- p.118 / Chapter 7.1 --- Methodology --- p.118 / Chapter 7.2 --- Evaluation Board --- p.119 / Chapter 7.3 --- Measurement Setup --- p.123 / Chapter 7.4 --- Experimental Results --- p.125 / Chapter 7.4.1 --- CMOS Injection Locked Oscillator --- p.125 / Chapter 7.4.2 --- LC Differential Voltage Controlled Oscillator --- p.128 / Chapter 7.4.3 --- LC Quadrature Voltage Controlled Oscillator --- p.132 / Chapter 7.5 --- Summary of Performance --- p.139 / Chapter Chapter 8 --- Conclusion --- p.142 / Chapter 8.1 --- Contribution --- p.142 / Chapter 8.2 --- Further Development --- p.143 / Chapter Chapter 9 --- Appendix --- p.145 / Chapter 9.1 --- Circuit Transformation --- p.145 / Chapter 9.2 --- Derivation of the Inductor Model with PGS --- p.146 / Chapter 9.2.1 --- "Inductance," --- p.146 / Chapter 9.2.2 --- "Series Resistance, Rs" --- p.146 / Chapter 9.2.3 --- Series Capacitance --- p.147 / Chapter 9.2.4 --- Shunt Oxide Capacitance --- p.147 / Chapter 9.3 --- Calculation of Phase Noise Using the Linear Time Variant Model --- p.148 / Chapter Chapter 10 --- Bibliography --- p.151

The design of high-performance, high-speed clock generation and distribution becomes challenging in terms of phase noise, jitter and power consumption, due to the fast development of communication and computing systems. Injection locking is a promising clocking technique since it can significantly improve the energy efficiency, suppress the phase noise of the ring oscillator, enable a fast startup and conveniently generate multiple time-interleaved phases. A quasi-linear model of injection-locked ring oscillator (ILRO) is utilized to mathematically formulate the frequency and time domain characteristics of the system, as well as the phase noise shaping and jitter tracking behavior. The settling behavior of ILRO is also exploited and shows a strong dependence on the locking range and the initial phase difference of the injected and the resultant oscillation signals. A forwarded-clock synchronization based on injection locking is designed for a 10 Gb/s photonic interconnect according to the specific features of optical links. A single clock recovery can be used for all the four channels, resulting in a large amount of power and area saving. The applications of sub-harmonic and super-harmonic injection locking in wireless communications for frequency multiplying and division are also discussed. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from Oct. 1, 2012 - Oct. 1, 2014

Based on a thesis in Electrical Engineering, 1966. / Bibliography: p.109-110. / Contract no. DA36-039-AMC-03200(E).

The feasibility and critical design parameters for the development of a thin-film evaporative cooling concept for a high energy, pulsed solid-state laser oscillator were investigated. The scope of the investigation was broad, and a multidisciplinary approach was employed. No contra-indicators for the feasibility of the proposed system were revealed. A 1-dimensional two-fluid was developed to model the hydrodynamic flow and heat transfer assuming a constant wall heat flux. This analysis produced nominal pressure drops for the flow required, indicating nominal power will be required to transport fluid across the crystal surface. Interfacial experiments reveal that the laser crystal material has a surface energy of approximately 30 mN/m, and is highly dispersive in nature. Design rules to allow for the orthotropic thermal expansion of the crystal rod surrounded by a thin metal sleeve were developed to support the design of a hermetic crystal-metal seal. The results indicate that commercially pure nickel produces minimal joint stresses for large thermal excursions.