Thesis (Ph. D.)--University of Washington, 2004. / Vita. Includes bibliographical references (leaves 102-109).

This thesis is concerned with the design and realisation of components for a new state of the art 94GHz Electron Spin Resonance (ESR) spectrometer capable of operating in both pulsed and CW modes. The complete spectrometer is designed to provide phase coherent 1kW peak power sub-nanosecond π/2 pulses having variable duration and repetition rate. The mm-wave response of a paramagnetic sample to these pulses is detected with a superheterodyne detector. Such a system would offer a step change in performance, promising unprecedented resolution and sensitivity. These aims should be compared with the performance of commercial (Bruker) instruments capable of delivering 200mW 30ns π/2 pulses. For this type of system, both the long term (thermal) and short term (phase) stability of oscillators and sources employed are extremely important. Consideration of phase noise, frequency, tunability and power output shows that multiplied sources offer substantial benefits compared to fundamental sources. A delay line discriminator method of phase noise measurement, suitable for use with the low frequency oscillators is described and implemented. This is extended to 94GHz using a down convertor with a quasi-optically stabilised Gunn oscillator. These tools are used to select an optimum oscillator-multiplier combination to produce a low noise 94GHz source. Anew method of pulse generation, which has produced +23dBm peak power 250ps rectangular and 115ps Gaussian envelope phase coherent pulses, is described. These are believed to be the shortest phase coherent pulses at 94GHz available. This system will be used to provide ns pulses suitable for amplification to 1kW using a Klystron amplifier. A heterodyne detector has been constructed which employs the same oscillator/multiplier techniques identified above to produce the required local oscillator signal. It is demonstrated that by careful consideration of multiplication factors a system employing one variable and one fixed oscillator allows all the signals required in the spectrometer to maintain phase coherence. It is demonstrated that the complete demodulator responds to pulses on a ns time scale and has a noise temperature of 737K.

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

Thèse (M.Eng.) -- Université du Québec à Chicoutimi, 2004. / Bibliogr.: f. [139]-140. Document électronique également accessible en format PDF. CaQCU

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2006. / Swaminathan, Madhavan, Committee Chair ; Cressler, John D., Committee Co-Chair ; Kenney, Stevenson J., Committee Member ; Peterson, Andrew, Committee Member ; Durgin, Gregory, Committee Member ; Sitaraman, Suresh, Committee Member.

The increasing demand for high-capacity and high-speed I/Os is pushing wireline and optical transceivers to a higher aggregate data rate. Multiple lanes of transceivers are monolithically integrated on a single system on chip (SoC), bringing more stringent requirements for the power consumption and area of a single transceiver. Clocking circuits directly determine the transceiver data rate and take a significant portion of the total power consumption. Power-efficient and high-speed data links rely on efficient and high-performance clock generation and distribution. Multi-phase clock generators (MPCGs) and phase interpolators (PIs) are two essential blocks in the local clock generator in each transceiver lane. MPCGs can generate multi-phase sampling clocks to increase the sampling rate of a fixed frequency, or they can generate multi-phase input clocks for the PIs to perform phase shifting. Their design also affects the schemes for global clock generation and distribution. 8-phase PIs improve the interpolation linearity compared to 4-phase PIs. However, their input 8-phase clock generation either requires power-hungry, multi-phase global clock distribution, or a complicated local 8-phase clock generator. Conventional clocking techniques have encountered the tradeoff of the jitter, power and phase accuracy for multi-phase clock generation. Moreover, 8-phase PIs also meet the linearity and speed bottleneck due to technology limitations. In this dissertation, we first discuss ring oscillators for multi-phase clock generation. The tradeoff of jitter and phase accuracy in ring oscillators locked by two-phase (0°/180°) injection is presented. This tradeoff is resolved by using a multi-phase injection-locked ring oscillator (MPIL-ROSC) for multi-phase clock generation. A quadrature delay-locked loop (QDLL) provides the coarse but low-jitter multi-phase injection signals to the MPIL-ROSC, and also tunes the MPIL-ROSC's self-oscillation frequency against process-voltage-temperature (PVT) variations. The MPCG is designed for 8-phase clock generation, and drives an 8-phase PI for clock interpolation. A 65-nm prototype chip shows that an MPIL-ROSC can generate low-jitter and highly accurate 8-phase clocks from 5 GHz to 8 GHz under a 1.1-V to 1.3-V supply variation. Moreover, a 7-bit PI driven by the MPIL-ROSC also achieves a peak-to-peak integral nonlinearity (INLpp) less than 1.90 LSB from 5 GHz to 8 GHz. To further improve the phase interpolation linearity and operation frequency range, a Twin phase interpolator (Twin PI) and a Delta quadrature delay-locked loop (Delta QDLL) are introduced. The phase nonlinearity of a 4-phase, linear-weight PI stems from approximating sinusoidal-weight summation with linear-weight summation. Consequently, the phase deviations are deterministic, sinusoidal, and repeat themselves among different interpolation quadrants. The Twin PI sums up the equalized-amplitude outputs from two, 4-phase PIs with their PI control codes offset by half of the INL "period". The INLs of two PIs have opposite signs to each other, and thus the summation cancels the majority of nonlinearity. The Twin PI achieves very high linearity across a wide operation bandwidth while only needing 4-phase (quadrature) input clocks, which eases the design of its preceding multi-phase clock generator and offers flexibility for global clock generation and distribution scheme. A Delta quadrature delay-locked loop is further proposed for low-jitter and wideband quadrature clock generation from the delay difference of two parallel delay paths with a background analog quadrature tuning loop. A 65-nm prototype chip demonstrates that a Delta QDLL generates quadrature clocks with an accuracy of 0.9° from 3.5 GHz to 11 GHz. The 7-bit Twin PI achieves less-than-1.45-LSB INLpp from 3.5 GHz to 11 GHz. At 7 GHz the INLpp is 0.72 LSB and the integrated fractional spur is as low as -41.7 dBc under -1429ppm clock modulation. To sum up, the proposed multi-phase injection-locked ring oscillators for multi-phase clock generation, and the combination of Twin phase interpolators and Delta quadrature delay-locked loop break the performance limitation of the state-of-the-art clocking circuits. The block-level innovation also offers opportunities to reconsider the global clocking scheme to save power and circuit area at the system level.

During strong ground shaking structures often become inelastic and respond hysteretically. Therefore, in this study some hysteretic models commonly used in seismic structural analysis are studied. In particular the characteristics of a popular endochronic model proposed by Bouc and Wen are examined in detail. In addition, analytical expressions have also been developed for most commonly used bilinear model as well as another model, herein called as the hyperbolic model.</p> / Master of Science

Cheng Sin-hang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 90-92). / Abstracts in English and Chinese. / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2 --- Theory of Oscillator Design --- p.4 / Chapter 2.1 --- Open-loop approach --- p.4 / Chapter 2.2 --- One-port approach --- p.6 / Chapter 2.3 --- Two-port approach --- p.9 / Chapter 2.4 --- Voltage controlled oscillator (VCO) design --- p.10 / Chapter 2.4.1 --- Active device selection and biasing --- p.11 / Chapter 2.4.2 --- Feedback circuit design --- p.15 / Chapter 2.4.3 --- Frequency tuning circuit --- p.20 / Chapter Chapter 3 --- Noise in Oscillators --- p.23 / Chapter 3.1 --- Origin of phase noise --- p.23 / Chapter 3.2 --- Impact of phase noise in communication system --- p.28 / Chapter 3.3 --- Phase noise consideration in VCO design --- p.30 / Chapter Chapter 4 --- Low Temperature Co-Fired Ceramic --- p.31 / Chapter 4.1 --- LTCC process --- p.31 / Chapter 4.1.1 --- LTCC fabrication process --- p.32 / Chapter 4.1.2 --- LTCC materials --- p.34 / Chapter 4.1.3 --- Advantages of LTCC technology --- p.35 / Chapter 4.2 --- Passive components realization in LTCC --- p.37 / Chapter 4.2.1 --- Capacitor --- p.37 / Chapter 4.2.2 --- Inductor --- p.42 / Chapter Chapter 5 --- High-Q LTCC Resonator Design --- p.47 / Chapter 5.1 --- Definition of Q-factor --- p.47 / Chapter 5.2 --- Stripline --- p.50 / Chapter 5.3 --- Power losses --- p.52 / Chapter 5.4 --- Laminated stripline resonator design --- p.53 / Chapter 5.4.1 --- λ/4 resonator structure --- p.57 / Chapter 5.4.2 --- Meander-line resonator structure --- p.60 / Chapter 5.4.3 --- Bi-metal-layer resonator structure --- p.63 / Chapter Chapter 6 --- LTCC Voltage Controlled Oscillator Design --- p.67 / Chapter 6.1 --- Circuit design --- p.67 / Chapter 6.2 --- Output filter --- p.68 / Chapter 6.3 --- Embedded capacitor --- p.71 / Chapter 6.4 --- VCO layout and simulation --- p.72 / Chapter Chapter 7 --- Experimental Setup and Results --- p.77 / Chapter 7.1 --- Measured Result: LTCC resonators --- p.77 / Chapter 7.1.1 --- Experimental results --- p.79 / Chapter 7.2 --- Measured results: LTCC voltage controlled oscillators --- p.83 / Chapter Chapter 8 --- Conclusion and Future Work --- p.88 / Reference List --- p.90 / Appendix A: TRL calibration method --- p.93 / Appendix B: Q measurement --- p.103 / Appendix C: Q-factor extraction program listing --- p.109 / Chapter 1. --- Function used to calculate Q from s-parameter --- p.109 / Chapter 2. --- Function used to calculate Q from z-parameter --- p.111

Yip Kim-fung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 95-100). / Abstracts in English and Chinese. / Abstract --- p.I / Acknowledgement --- p.III / Table of Contents --- p.IV / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objective --- p.6 / Chapter Chapter 2 --- Theory of Oscillators --- p.7 / Chapter 2.1 --- Oscillator Design --- p.7 / Chapter 2.1.1 --- Loop-Gain Method --- p.7 / Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8 / Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10 / Chapter Chapter 3 --- Noise Analysis --- p.15 / Chapter 3.1 --- Origin of Noise Sources --- p.16 / Chapter 3.1.1 --- Flicker Noise --- p.16 / Chapter 3.1.2 --- Thermal Noise --- p.17 / Chapter 3.1.3 --- Noise Model of Varactor --- p.18 / Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19 / Chapter 3.2 --- Derivation of Resonator --- p.19 / Chapter 3.3 --- Phase Noise Model --- p.22 / Chapter 3.3.1 --- Leeson's Model --- p.23 / Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24 / Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26 / Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31 / Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33 / Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33 / Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35 / Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37 / Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39 / Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42 / Chapter 4.1 --- Device Modeling --- p.42 / Chapter 4.1.1 --- FET model --- p.42 / Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46 / Chapter 4.1.3 --- Planar Inductor --- p.48 / Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50 / Chapter 4.1.5 --- Inductor Layout Consideration --- p.54 / Chapter 4.1.6 --- CMOS RF Varactor --- p.55 / Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57 / Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59 / Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59 / Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59 / Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61 / Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62 / Chapter 5.1.4 --- Output buffer --- p.63 / Chapter 5.1.5 --- Biasing Circuitry --- p.64 / Chapter 5.2 --- Spiral Inductor Design --- p.65 / Chapter 5.3 --- Determination of W/L ratio of FET --- p.67 / Chapter 5.4 --- Varactor Design --- p.68 / Chapter 5.5 --- Layout (Cadence) --- p.69 / Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74 / Chapter Chapter 6 --- Experimental Results and Discussion --- p.76 / Chapter 6.1 --- Measurement Setup --- p.76 / Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81 / Chapter 6.2.1 --- Output Spectrum --- p.81 / Chapter 6.2.2 --- Phase Noise Performance --- p.82 / Chapter 6.2.3 --- Tuning Characteristic --- p.83 / Chapter 6.2.4 --- Microphotograph --- p.84 / Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85 / Chapter 6.3.1 --- Output Spectrum --- p.85 / Chapter 6.3.2 --- Phase Noise Performance --- p.86 / Chapter 6.3.3 --- Tuning Characteristic --- p.87 / Chapter 6.3.4 --- Microphotograph --- p.88 / Chapter 6.4 --- Comparison of Measured Results --- p.89 / Chapter 6.4.1 --- Phase Noise Performance --- p.89 / Chapter 6.4.2 --- Tuning Characteristic --- p.90 / Chapter Chapter 7 --- Conclusion and Future Work --- p.93 / Chapter 7.1 --- Conclusion --- p.93 / Chapter 7.2 --- Future Work --- p.94 / References --- p.95 / Author's Publication --- p.100 / Appendix A --- p.101 / Appendix B --- p.104 / Appendix C --- p.106

[Truncated abstract] This thesis is split into two parts. In part one; A 50 K dual mode oscillator, the aim of the project was to build a 50 K precision oscillator with frequency stability on the order of 1014 from 1 to 100 seconds. A dual-mode temperature compensation technique was used that relied on a turning point in the frequency-temperature relationship of the difference frequency between two orthogonal whispering gallery modes in a single sapphire crystal. A cylindrical sapphire loaded copper cavity resonator was designed, modelled and built with a turning point in the difference frequency between an E-mode and H-mode pair at approximately 52.5 K . . . The frequencies and Q-factors of whispering spherical modes in the 3-12 GHz range in the fused silica resonator are measured at 6, 77 and 300 K and the Q-factor is used to determine the loss tangent at these temperatures. The frequency and Q-factor temperature dependence of the TM2,1,2 whispering gallery mode at 5.18 GHZ is used to characterise the loss tangent and relative permittivity of the fused silica from 4-300 K. Below 22 K the frequency-temperature dependence of the resonator was found to be consistent with the combined effects of the thermal properties of the dielectric and the influence of an unknown paramagnetic impurity, with a spin resonance frequency at about 138 ± 31 GHz. Below 8 K the loss tangent exhibited a 9th order power law temperature dependence, which may be explained by Raman scattering of Phonons from the paramagnetic impurity ions. A spherical Bragg reflector resonator made from multiple concentric dielectric layers loaded in a spherical cavity that enables confinement of field in the centre of the resonator is described. A set of simultaneous equations is derived that allow the calculation of the required dimensions and resonance frequency for such a resonator and the solution is confirmed using finite element analysis. A spherical Bragg reflector resonator is constructed using Teflon and free-space as the dielectric materials. A Q-factor of 22,000 at 13.87 GHz was measured and found to compare well with the design values.