One of the most critical blocks in a wide-band continuous time sigma delta (CTSD) analog-to-digital converter (ADC) is the loop filter. For most loop filter topologies, the performance of the filter depends largely on the performance of the operational amplifiers (op-amps) used in the filter. The op-amps need to have high linearity, low noise and large gain over a wide bandwidth. In this work, the impact of op-amp parameters like noise and linearity on system level performance of the CTSD ADC is studied, and the design specifications are derived for the op-amps. A new class-AB bias scheme, which is more robust to process variations and has an improved high frequency response over the conventional Monticelli bias scheme, is proposed. A biquadratic filter which forms the input stage of a 5th order low pass CTSD ADC is used as a test bench to characterize the op-amp performance. The proposed class-AB output stage is compared with the class-AB output stage with Monticelli bias scheme and a class-A output stage with bias current reuse. The filter using the new op-amp architecture has lower power consumption than the other two architectures. The proposed class AB bias scheme has better process variation and mismatch tolerance compared to the op-amp that uses conventional bias scheme.

The diploma thesis deals with the solution of output power amplifiers for home listening. There are mentioned basic terms and illustrated several well-known solutions of power amplifiers. Is described formation and possibilities to minimize transient distortion of output stage. For verification is implemented full-symmetrical output stage.

The target of this master’s thesis is to design a functional sample of radiofrequency power amplifier for short waves radio amateur bands and measure its basic parameters such as required input power, output power, output spectrum purity and efficiency. The construction is based on results of behavioral simulation of the amplifier’s model obtained from circuit simulator cadence™OrCAD 16. The amplifier ought to be later used as an output stage for a small radio amateur transceiver.

Master’s thesis deals with design of rail-to-rail second generation current conveyor in CMOS technology. Describes principles of function of different generations of current conveyors, as well as the basic principle of design of second generation current conveyor based on operational amplifier. Addresses circuit topology of input rail-to-rail stage and class AB output stage. The objective of this thesis is to design, characterize performance and create layout of second generation current conveyor with input common mode voltage rail-to-rail capability in ONSemi I3T25 technology.