When designing analog circuits, we must ultimately perform measurements on the fabricated chips to determine whether they work correctly or not. The test results are compared with simulation results to determine what the differences to the expected results are. Therefore, incremental improvement and redesign becomes possible. We can obtain highly important information from the test results, making circuit testing a very important aspect of the process of analog circuit design. Especially, measurements during the development phase may include internal circuit nodes which will not be accessible in a final design but are pinned out specifically in the development phase. Because the probing tools present capacitive loads to the circuit, these additional loads may affect the analog circuits‟ response, especially in a high frequency range. Therefore, decreasing influence of capacitive loads of the probing tools in the testing environment is very important. We use analog buffers to separate the analog circuit node from the probing tools. Therefore, the buffer becomes a very important block in analog circuit testing [1-3]. For adapting to different testing environments, this thesis examines three different types of buffer which are designed using a partially modular method [4, 5]. All buffers provide a DC to 1 MHz bandwidth. The first buffer module provides a -1.3 V~1.3 V signal range driving 25 pf~85 pf capacitive loads; the second buffer has a -0.8 V~0.8 V range with for 5 pf~25 pf loads; the third buffer yields -0.5 V~0.5 V range with 1 pf~5 pf loads. The circuit design is discussed and simulated results are presented. Finally, measured results are reported for an open-loop output stage with near unity gain (buffer three). This circuit was previously fabricated in 0.35 £gm CMOS technology.

An FM transmitter becomes the new feature in recent portable electronic development. A low power, integrable FM transmitter filter IC is required to meet the demand of FM transmitting feature. A low pass filter using harmonic rejection technique along with a low power class-AB output buffer is designed to meet the current market requirements on the FM transmitter chip. A harmonic rejection filter is designed to filter FM square wave signal from 70MHz to 110MHz into FM sine wave signal. Based on Fourier series, the harmonic rejection technique adds the phase shifted square waves to achieve better THD and less high frequency harmonics. The phase shifting is realized through a frequency divider, and the summation is implemented through a current summation circuit. A RC low pass filter with automatic tuning is designed to further attenuate unwanted harmonics. In this work, the filter's post layout simulation shows -53dB THD and harmonics above 800MHz attenuation of -99dB. The power consumption of the filter is less than 0.7mW. Output buffer stage is implemented through a resistor degenerated transconductor and a class-AB amplifier. Feedforward frequency compensation is applied to compensate the output class-AB stage, which extends the amplifier's operating bandwidth. A fully balanced class-AB driver is proposed to unleash the driving capability of common source output transistors. The output buffer reaches -43dB THD at 110MHz with 0.63Vpp output swing and drives 1mW into 50 load. The power consumption of the output buffer is 7.25mW. By using harmonic rejection technique, this work realizes the 70MHz-110MHz FM carrier filtering using TSMC 0.18um nominal process. Above 800MHz harmonics are attenuated to below -95dB. With 1.2V supply, the total power consumption including output buffer is 7.95mW. The total die area is 0.946mm2.

One of the most critical blocks in a wide-band continuous time sigma delta (CTSD) analog-to-digital converter (ADC) is the loop filter. For most loop filter topologies, the performance of the filter depends largely on the performance of the operational amplifiers (op-amps) used in the filter. The op-amps need to have high linearity, low noise and large gain over a wide bandwidth. In this work, the impact of op-amp parameters like noise and linearity on system level performance of the CTSD ADC is studied, and the design specifications are derived for the op-amps. A new class-AB bias scheme, which is more robust to process variations and has an improved high frequency response over the conventional Monticelli bias scheme, is proposed. A biquadratic filter which forms the input stage of a 5th order low pass CTSD ADC is used as a test bench to characterize the op-amp performance. The proposed class-AB output stage is compared with the class-AB output stage with Monticelli bias scheme and a class-A output stage with bias current reuse. The filter using the new op-amp architecture has lower power consumption than the other two architectures. The proposed class AB bias scheme has better process variation and mismatch tolerance compared to the op-amp that uses conventional bias scheme.

This thesis starts with a discussion of different classes of operation of power amplifiers (PAs). Comparing advantages and disadvantages of these classes, class AB is chosen as the best initial candidate for the design of broadband PA. Different methods for design of matching networks are first discussed. Some of them fall into the group of narrowband matching networks, while others are suitable for a broadband context. Broadband design methodologies are categorized into two groups of real-to-real transformations and complex-to-real transformations. Complex-to-real transformations are the most useful methods for this project, since design of power amplifiers deals with complex loads rather than just real loads. The design of broadband matching networks exploiting filter theory is presented in this thesis for synthesizing broadband and highly efficient power amplifiers (PAs). Starting with sets of optimum impedances over the targeted frequency band, the matching networks are designed using a systematic approach. The effects of load termination at the 2nd and 3rd harmonic on the PA performance (efficiency) are studied. The significance of proper termination, especially at the 2nd harmonic, is highlighted. To prevent further complication of the design process, though, specific harmonic termination (stubs) is avoided and special arrangement of the matching network (position of the bias network) is preferred, as it is found to lead to acceptable efficiency. Two PA prototypes were designed with the proposed methodology using 25W GaN devices. The designs targeted two frequency bands: 1.8 to 2.2 GHz (20% BW) and 1.8 to 2.7 GHz (40% BW). For the former, drain efficiency (DE) of 70% (+/–5%) and output power of 45.5 dBm (+/- 1.0dB) was measured while the latter achieved very promising efficiency of about 60% over the entire bandwidth.

This thesis starts with a discussion of different classes of operation of power amplifiers (PAs). Comparing advantages and disadvantages of these classes, class AB is chosen as the best initial candidate for the design of broadband PA. Different methods for design of matching networks are first discussed. Some of them fall into the group of narrowband matching networks, while others are suitable for a broadband context. Broadband design methodologies are categorized into two groups of real-to-real transformations and complex-to-real transformations. Complex-to-real transformations are the most useful methods for this project, since design of power amplifiers deals with complex loads rather than just real loads. The design of broadband matching networks exploiting filter theory is presented in this thesis for synthesizing broadband and highly efficient power amplifiers (PAs). Starting with sets of optimum impedances over the targeted frequency band, the matching networks are designed using a systematic approach. The effects of load termination at the 2nd and 3rd harmonic on the PA performance (efficiency) are studied. The significance of proper termination, especially at the 2nd harmonic, is highlighted. To prevent further complication of the design process, though, specific harmonic termination (stubs) is avoided and special arrangement of the matching network (position of the bias network) is preferred, as it is found to lead to acceptable efficiency. Two PA prototypes were designed with the proposed methodology using 25W GaN devices. The designs targeted two frequency bands: 1.8 to 2.2 GHz (20% BW) and 1.8 to 2.7 GHz (40% BW). For the former, drain efficiency (DE) of 70% (+/–5%) and output power of 45.5 dBm (+/- 1.0dB) was measured while the latter achieved very promising efficiency of about 60% over the entire bandwidth.

No description available.

The work deals with the analog design of low-voltage and low-power differential difference amplifier DDA with adaptive differential input stage, second stage class AB, improved by a self – cascode to achieve higher gain and slew rate. Conventional and unconventional techniques, and methods for low-voltage and low-power design are presented. The finished design of the differential difference amplifier DDA with the analyzed results is presented. Design of a Butterwortho low-pass filter of the sixth order based on DDA with Sallen Key topology and design of a multifunctional ARC filter based on DDA.

The diploma thesis deals with the solution of output power amplifiers for home listening. There are mentioned basic terms and illustrated several well-known solutions of power amplifiers. Is described formation and possibilities to minimize transient distortion of output stage. For verification is implemented full-symmetrical output stage.

Universal Mobile Telecommunications Systems (UMTS) is the preferred third generation (3G) communication standard for mobile communications and will provide worldwide coverage, a convenient software technology and very high data rate. The high data rate, especially, requires the use of bandwidth-efficient modulation schemes such as Quadrature Phase Shift Keying (QPSK). But modulation schemes such as QPSK need, in turn, a very linear power from the output of the transmitter power amplifier in order to meet the spectral requirements. A linear power amplifier, traditionally, has very low energy efficiency. Poor energy efficiency directly affects operational costs and causes thermal heating issues in base station transmitters. Thus the power amplifier designer is forced to trade-off between linearity and efficiency. As a result of this trade-off a Class-AB power amplifier is most often used in QPSK based systems. Class-AB power amplifiers provide acceptable linearity at efficiency values around 45-50% typically. This compromise is not a satisfactory solution but is inevitable while using traditional power amplifier design techniques. This thesis details the use of a Class-F amplifier with carefully chosen bias points and harmonic traps to overcome this problem. Class-F amplifiers are usually considered as very high efficiency (80% or more power-added efficiency) amplifiers where the high efficiency is obtained through the use of harmonic traps (L-C filters or quarter-wavelength transmission lines), which provide suitable terminations (either open or short) for the harmonics generated. By doing this, a square wave drain voltage and a peaked half-sinusoidal drain current out-of-phase by 180 are produced. Since only a drain voltage or a drain current exists at any given time, the power dissipation is ideally zero resulting in 100% theoretical efficiency. These very high efficiency values are usually associated with poor linearity. However the linearity can be improved to meet the design standards but compromising on efficiency. Even after this is done, efficiencies are usually 10 to 15% greater than a traditional Class AB power amplifier with similar linearity performance. Thus efficiency can be improved without affecting linearity by the use of Class-F power amplifiers. In order to verify this theory, a Class-AB and a Class-F power amplifier are designed using Motorola's high voltage laterally diffused metal oxide semiconductor (LDMOS) transistor. The choice of bias points and the design of the harmonic traps are very critical for the Class-F performance and hence were designed after careful consideration. The designs were simulated on Agilent's Advanced Design System (ADS) and the simulated results were compared for three different power levels namely, the peak power, 3 dB below peak power and 6 dB below peak power. At all of these power levels it was noted that the Class-F and Class-AB power amplifiers have very similar linearity performance whereas the Class-F power amplifiers show about 10% improvement in efficiency in comparison to the Class-AB power amplifiers. / Master of Science

Yes / Fourth generation systems require the use of both amplitude and phase modulation to efficiently utilize the available spectrum and to obtain high data rates, hence imposing stringent requirements on the power amplifier in terms of efficiency and linearity and requires the power amplifier to operate linearly and efficiently. The B3G base station transceiver Doherty power amplifier was designed to operate over the frequency range of 3.47GHz to 3.53GHz mobile WiMAX band using Freescale¿s N-Channel Enhancement-Mode Lateral MOSFET Transistor, MRF7S38010HR3; The performances of the Doherty amplifier are compared with that of the conventional Class AB amplifier. The results of 43 dBm output power and 66% power added efficiency are achieved.