This thesis consists of two parts. Part 1 introduces the characteristics of Class E power amplifier. Part 2 is focused on the implementation of Class E power amplifier for 2.4GHz Bluetooth applications. The design procedure follows the theory of class E power amplifier, and is implemented in MMICs and modules. For MMICs, the GaAs HBT foundry services are provided by the GCTC Ltd. and WIN Ltd.. Under single supply voltage of 3.3V and the output power of 20dBm, two designed MMICs have gain 23dB and 11dB, and power added efficiency (PAE) 57% and 72%, respectively. For Hybrid modules, RF transistors are provided by the Filtronic Ltd.. Under the same supply voltage of 3.3V, the measured output power, gain, and power added efficiency are 20 dBm, 25dB, and 75% respectively. Compared with the other types of power amplifiers on the market, Class E power amplifier has higher power added efficiency, and thus can increase the using time of communication system.

Universal Mobile Telecommunications Systems (UMTS) is the preferred third generation (3G) communication standard for mobile communications and will provide worldwide coverage, a convenient software technology and very high data rate. The high data rate, especially, requires the use of bandwidth-efficient modulation schemes such as Quadrature Phase Shift Keying (QPSK). But modulation schemes such as QPSK need, in turn, a very linear power from the output of the transmitter power amplifier in order to meet the spectral requirements. A linear power amplifier, traditionally, has very low energy efficiency. Poor energy efficiency directly affects operational costs and causes thermal heating issues in base station transmitters. Thus the power amplifier designer is forced to trade-off between linearity and efficiency. As a result of this trade-off a Class-AB power amplifier is most often used in QPSK based systems. Class-AB power amplifiers provide acceptable linearity at efficiency values around 45-50% typically. This compromise is not a satisfactory solution but is inevitable while using traditional power amplifier design techniques. This thesis details the use of a Class-F amplifier with carefully chosen bias points and harmonic traps to overcome this problem. Class-F amplifiers are usually considered as very high efficiency (80% or more power-added efficiency) amplifiers where the high efficiency is obtained through the use of harmonic traps (L-C filters or quarter-wavelength transmission lines), which provide suitable terminations (either open or short) for the harmonics generated. By doing this, a square wave drain voltage and a peaked half-sinusoidal drain current out-of-phase by 180 are produced. Since only a drain voltage or a drain current exists at any given time, the power dissipation is ideally zero resulting in 100% theoretical efficiency. These very high efficiency values are usually associated with poor linearity. However the linearity can be improved to meet the design standards but compromising on efficiency. Even after this is done, efficiencies are usually 10 to 15% greater than a traditional Class AB power amplifier with similar linearity performance. Thus efficiency can be improved without affecting linearity by the use of Class-F power amplifiers. In order to verify this theory, a Class-AB and a Class-F power amplifier are designed using Motorola's high voltage laterally diffused metal oxide semiconductor (LDMOS) transistor. The choice of bias points and the design of the harmonic traps are very critical for the Class-F performance and hence were designed after careful consideration. The designs were simulated on Agilent's Advanced Design System (ADS) and the simulated results were compared for three different power levels namely, the peak power, 3 dB below peak power and 6 dB below peak power. At all of these power levels it was noted that the Class-F and Class-AB power amplifiers have very similar linearity performance whereas the Class-F power amplifiers show about 10% improvement in efficiency in comparison to the Class-AB power amplifiers. / Master of Science

The number of mobile wireless devices on the market has increased substantially over the last decade. The frequency spectrum has become crowded due to the number of devices demanding radio traffic and new modulation schemes have been developed to accommodate the number of users. These new modulation schemes have caused very poor efficiencies in power amplifiers for wireless transmission systems due to high peak-to-average power ratios (PAPR). This thesis first presents the issue with classical power amplifiers in modern modulation systems. A brief overview of current attempts to mitigate this issue is provided. A new RF power amplifier topology is then presented with supporting simulations. The presented amplifier topology utilizes the concept of negative conductance and load modulation. The amplifier operates in two stages, a low power stage and a high power stage. A negative conductance amplifier is utilized during peak power transmission to modulate the load presented to the input amplifier. This topology is shown to greatly improve the power added efficiency of power amplifiers in systems with high PAPR.

In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called ¿future internet¿ paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / A conventionally designed radio frequency amplifier operated in its linear region exhibits low DC to RF conversion efficiency. Typically, for a power amplifier designed for digital modulation applications, the amplifier is operated “backed-off” from its P1dB point by a factor of 10 or -10 dB. The typical linear amplifier is biased for either Class A or Class A/B operation depending on the acceptable design trade-offs between efficiency and linearity between these two methods. A novel design approach to increasing the efficiency of a linear RF power amplifier using a modified Odd-Way Doherty technique is presented in this paper. The design was simulated, built and then tested. The design yields improvements in efficiency and linearity.

In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called 'future internet' paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

<p>The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation.</p><p>The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done.</p><p>The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W.</p><p>A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.</p>

The purpose of this master thesis was to study if the drain efficiency of power amplifiers can be maintained at power back off using a technique called load modulation. The amplifier classes studied are E, F and D-1. The target figure was to obtain a 10 to 12 dB dynamic range of amplitude with reasonable efficiency. Studies of power amplifiers have been made to understand how power is generated. Several different load modulation networks have been evaluated. Attempts to derive design equations for the modulation networks have also been done. The thesis work was carried out with simulations in ADS 2006. As active devices commercially available bare-die transistor models have been used. The power rating of the dies are 15 W. A dynamic range of amplitude of over 15 dB has been achieved with drain efficiency greater than 60 percent. The peak output power is in the 40 – 45 dBm range.

Phased array element RF front ends typically use single pole double throw (SPDT) switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, the physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This work demonstrates a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multi-variable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the power amplifier (PA) and the low noise amplifier (LNA) while maximizing power transfer efficiency and minimizing dissipative losses in each (transmit or receive) mode of operation. Three PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. The first example design in 32SOI CMOS leverages PA and LNA circuits that already include 50 Ω matching networks at both input and output. The second example design in 8XP SiGe develops the PA and LNA circuits and integrates the PA output and LNA input matching networks into the PALNA matching network that connects the PA and the LNA. The third design in 32SOI CMOS leverages the loss-aware PALNA design methodology to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes, this dissertation also presents an efficient, switch-based T/R circuit design in 32SOI CMOS technology, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits. / Doctor of Philosophy / In military and commercial applications, phased arrays are devices primarily used to achieve focusing and steering of transmitted or received electromagnetic energy. Phased arrays consist of many elements, each with an ability to both transmit and receive radio frequency (RF) signals. Each element incorporates a power amplifier (PA) for transmit and a low noise amplifier (LNA) for receive, which are typically connected using a single pole double throw (SPDT) switch or a circulator with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased arrays exploit the latest technological advances in circuit integration and their frequencies of operation increase, physical size and performance degradations associated with switches and circulators can present challenges in meeting system performance and size/weight/power (SWAP) requirements. This dissertation provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits where the switches and circulators are replaced by carefully designed power amplifier/low-noise amplifier (PALNA) impedance matching networks. In the switchless T/R circuits, the design goals of maximum power efficiency and minimum noise in transmit and receive, respectively, are achieved through impedance matching that is optimal and low-loss in both modes of operation simultaneously. Three distinct PALNA example designs at W-band are presented in this dissertation, each following a distinct design methodology. With each new design, lessons learned are leveraged and design methodologies are enhanced. The first example design leverages already available PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to guarantee optimum impedance match in receive and transmit mode of operation. The second example design develops new PA and LNA circuits and connects them using 50 Ω transmission lines whose lengths are designed to simultaneously achieve optimum impedance matching for maximum power efficiency in transmit mode of operation and lowest noise in receive mode of operation. The third design leverages a loss-aware PALNA design methodology, a multi-variable optimization procedure, to develop a PALNA that achieves simulated maximum power added efficiency of 18 % in transmit and noise figure of 7.5 dB in receive at 94 GHz, which is beyond the published state-of-art for T/R circuits. In addition, for comparison purposes with the third PALNA design, this dissertation also presents an efficient, switch-based T/R circuit design, which achieves a simulated maximum power added efficiency of 15 % in transmit and noise figure of 6.5 dB in receive at 94 GHz, which is also beyond the published state-of-art for T/R circuits.