No description available.

No description available.

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power amplifier and linearizer design techniques. Dynamically varying the load impedance and bias point of a transistor according to the varying envelope of the incoming RF signal also known as Dynamic Load Modulation (DLM) and Dynamic Supply Modulation (DSM), respectively, are two separate methods for improving the efficiency in power amplifier design. In this dissertation, a combination of both variable gate bias and tunable load concepts is applied in an amplifier structure consisting of two transistors in parallel. A novel computer aided design methodology is proposed for careful selection of the load and biasing points of the individual transistors. The method which is based on load-pull analysis performs sweeps on the gate bias voltages of the active devices and input drive level of the amplifier in order to obtain ranges of biases that result in the generation of IMD sweet spots. Following that, the amplifier is designed employing the load line theory and bias switching at the same time in order to enhance the efficiency in reduced drive levels while extending the output 1 dB compression point to higher values at higher drives. Tunable matching networks are implemented utilizing varactor stacks in a &Pi / con

Advanced digital modulation schemes used in the wireless applications, result in the modulated RF signals with high peak to average power ratio which requires linear amplification. On the other hand, the demand for a longer talk time with less battery volume and weight, especially in hand-held radio units, necessitate more power efficient methods to be utilized in power amplifier design. But improved linearity and efficiency have always been contradicting requirements demanding innovative power ampli

The ultimate goal of the modern wireless communication industry is the full integration of digital, analog, and radio frequency (RF) functions. The most successful solution for such demands has been complementary metal oxide semiconductor (CMOS) technology, thanks to its cost-effective material and great versatility. Power amplifier (PA), the biggest bottleneck to integrate in a single-chip transceiver in wireless communications, significantly influences overall system performance. Recent advanced wireless communication systems demand a power amplifier that can simultaneously support different communication standards. A fully integrated single-chip tunable CMOS power amplifier is the best solution in terms of the cost and level of integration with other functional blocks of an RF transceiver. This work, for the first time, proposes a fully integrated band-switchable RF power amplifier by using a novel approach towards switching the matching networks. In this approach, which is called Bit Optimized Reconfigurable Network (BORN), two matching networks which can be controlled by digital bits will provide three operating frequency bands for the power amplifier. In order to implementing the proposed BORN PA, a robust high-power RF switch is presented by using resistive body floating technique and 6-terminal triple-well NMOS. The proposed BORN PA delivers measured saturated output power (Psat) of 21.25/22.25/ 23.0dBm at 960MHz/1317MHz/1750MHz, respectively. Moreover, the proposed BORN PA provides respective 3-dB bandwidth of 400MHz/425MHz/550MHz, output 1-dB compression point (P1dB) of 19.5dBm/20.0dBm/21.0dBm, and power-added efficiency (PAE) of 9/11/13% at three targeted frequency bands, respectively. The promising results show that the proposed BORN PA can be a practical solution for RF multiband applications in terms of the cost and level of integration with other functional blocks of an RF transceiver.

A mathematical model for a multiple-input multiple-output radar system is presented. The model is used to track signals through the system in order to identify the impact of antenna array mutual coupling on radar system performance. Simulations using the model provide quantitative assessment of the performance degradation as a function of antenna coupling strength. Specifically, the results show that coupling can cause a target to appear at an angle notably different than its actual angle and can cause an increase in the side lobe level. A compensation technique is presented that completely removes these effects for practical levels of coupling. However, it is highly sensitive to inaccurate measurements of the system as well as time-varying system components. The technique may degrade the system performance further in some cases. Matching network design techniques and their impact on the system performance are also examined. For some levels of coupling they provide marginal improvement but may decrease system performance for other levels.

Dans le contexte de développement de produits sans-contact communiquant à très haut débit, dît systèmes VHBR (Very High Bit Rate), il s’avère que les cartes ou passeports VHBR, télé-alimentés à partir du lecteur qui communique avec eux, sont contraints de fonctionner avec une alimentation bien plus faible que les produits communiquant à des débits standards. Pour répondre à cette problématique de manque de puissance d’alimentation, il a été nécessaire de commencer par reprendre la théorie des lignes en l'orientant de manière à ce qu'elle permette de quantifier les transferts de puissance entre une source et une charge séparées par un média quelconque. Ensuite, ce nouveau moyen de quantification des transferts de puissance a été utilisé pour faire de l'aide à la conception des lecteurs VHBR. Ensuite, ce travail de recherche se concentre sur les cartes ou passeports VHBR. En effet, pour permettre à un tel système sans contact de fonctionner de manière télé-alimentée dans un environnement où la puissance disponible est réduite, il faut optimiser sa conception. Les solutions proposées ici consistent à déterminer la géométrie des antennes inductives qui optimisent la récupération d'énergie et le transfert de puissance vers la puce d'une carte VHBR. Ainsi, les travaux présentés dans ce manuscrit apportent des solutions globales à cette problématique de récupération d'énergie dans les objets connectés que sont les systèmes sans contact, en décrivant des méthodes de conception qui permettent d'une part de limiter les pertes de puissance au sein des lecteurs VHBR, et d'autre part d'optimiser la récupération d'énergie au sein des cartes VHBR. / The research work presented in this thesis provides solutions to help industrials to better design RFID readers and RFID tags that implement VHBR (Very High Bit Rate) protocols. Indeed, VHBR technology has a large drawback on the functionning of RFID tags as it lowers the energy available to supply the tag. First, this research work focuses on RFID reader design, and especially matching networks design. After describing a new way of assessing power transfer in Radio Frequency systems, it is shown that T matching networks as thoses proposed in ISO/IEC 10373-6 give the best results in terms of power transfer and signal integrity. Thus, a design method is proposed to correctly choose the three T matching network components that will optimize the power transfer and still meet the signal integrity requirements.Second, this thesis will focus on the design of RFID tags, by describing a new tag's antenna design method that optimize the energy harvested by the antenna and meanwhile reduce the power reflections between the antenna and the tag's chip. This design method is based on new explicit formula that compute a rectangular planar antenna inductance as a function of its geometric characteristics. This method showed very accurate results, and can become an interesting tool for industrials to speed up and optimize their antenna design procedure.Finally, a platform that measures RFID chip's impedance in every state of the chip has been designed, even during load modulation communication. The accuracy of this tool and its importance in order to achieve a good antenna design confer it a great usefulness.

In today's digital world, information and communication technology accounts for 3% and 2% of the global power consumption and CO2 emissions respectively. This alarming figure is on an upward trend, as future telecommunications systems and handsets will become even more power hungry since new services with higher bandwidth requirements emerge as part of the so called ¿future internet¿ paradigm. In addition, the mobile handset industry is tightly coupled to the consumer need for more sophisticated handsets with greater battery lifetime. If we cannot make any significant step to reducing the energy gap between the power hungry requirements of future handsets, and what battery technology can deliver, then market penetration for 4G handsets can be at risk. Therefore, energy conservation must be a design objective at the forefront of any system design from the network layer, to the physical and the microelectronic counterparts. In fact, the energy distribution of a handset device is dominated by the energy consumption of the RF hardware, and in particular the power amplifier design. Power amplifier design is a traditional topic that addresses the design challenge of how to obtain a trade-off between linearity and efficiency in order to avoid the introduction of signal distortion, whilst making best use of the available power resources for amplification. However, the present work goes beyond this by investigating a new line of amplifiers that address the green initiatives, namely green power amplifiers. This research work explores how to use the Doherty technique to promote efficiency enhancement and thus energy saving. Five different topologies of RF power amplifiers have been designed with custom-made signal splitters. The design core of the Doherty technique is based on the combination of a class B, class AB and a class C power amplifier working in synergy; which includes 90-degree 2-way power splitter at the input, quarter wavelength transformer at the output, and a new output power combiner. The frequency range for the amplifiers was designed to operate in the 3.4 - 3.6 GHz frequency band of Europe mobile WiMAX. The experimental results show that 30dBm output power can be achieved with 67% power added efficiency (PAE) for the user terminal, and 45dBm with 66% power added efficiency (PAE) for base stations which marks a 14% and 11% respective improvement over current stateof- the-art, while meeting the power output requirements for mobile WiMAX applications.

No description available.

This research presents design techniques for a linear power amplifier with high efficiency in wireless handsets. The power amplifier operates with high efficiency at the saturated output power, maintains high linearity with enhanced efficiency at back-off power levels, and covers a broadband frequency response. The amplifier is thus able to operate in multiple modes (2G/2.5G/3G/4G). The design techniques provide contributions to current research in handset power amplifiers, especially to the converged power amplifier architecture, to reduce the number of power amplifiers within the handset while covering all standards and frequency bands around the globe. Three main areas of interest in power amplifier design are investigated: high power efficiency; high linearity; and broadband frequency response. Multiple techniques for improving the efficiency are investigated with the focus on maintaining linear operation. The research applies a new technique to the handset industry, class-J, to improve the power efficiency while avoiding the practical issues that hinder the typical techniques (class-AB and class-F). Class-J has been implemented using GaN FET in high power applications. To our knowledge, this work provides the first implementation of class-J using GaAs HBT in a handset power amplifier. The research investigates the linearity, and the nature and causes of nonlinearities. Multiple concepts for improving the linearity are presented, such as avoiding odd-degree harmonics, and linearizing the relationship between the output current and the input voltage of the amplifier at the fundamental frequency. The concept of bias depression in HBT transistors is introduced with a bias circuit that reduces the bias-offset effect to improve linearity at high output power. A design methodology is presented for broadband matching networks, including the component loss. The methodology offers a quick and accurate estimation of component values, giving more degrees of freedom to meet the design specifications. It enables a trade-off among high out-of-band attenuation, number/size of components, and power loss within the network. Although the main focus is handset power amplifiers, most of the developed techniques can be applied to a wide range of power amplifiers. / Ph. D.