The first topic of this thesis presents a one-time programmable (OTP) ROM using a standard logic CMOS process. A high voltage is applied to the gate-oxide to breakdown the MOS in the ROM-cell. It results in a low resistance compared to that of unprogrammed cells. Therefore, we can realize an OTP ROM with this characteristic on a CMOS logic ASIC or SOC. The second topic is a DDFS (Direct Digital Frequency Synthesizer) implementation. A straight-line approximation algorithm for sinusoid with compensation is adopted in the proposed DDFS such that the accuracy could be maintained and the cost is reduced. Most important of all, the proposed CMOS OTP ROM is employed as the sinusoidal look-up ROM table to simplify the ROM fabrication without any additional process step.

<p>The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes.</p><p>This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.</p>

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The ultimate goal of the modern wireless communication industry is the full integration of digital, analog, and radio frequency (RF) functions. The most successful solution for such demands has been complementary metal oxide semiconductor (CMOS) technology, thanks to its cost-effective material and great versatility. Power amplifier (PA), the biggest bottleneck to integrate in a single-chip transceiver in wireless communications, significantly influences overall system performance. Recent advanced wireless communication systems demand a power amplifier that can simultaneously support different communication standards. A fully integrated single-chip tunable CMOS power amplifier is the best solution in terms of the cost and level of integration with other functional blocks of an RF transceiver. This work, for the first time, proposes a fully integrated band-switchable RF power amplifier by using a novel approach towards switching the matching networks. In this approach, which is called Bit Optimized Reconfigurable Network (BORN), two matching networks which can be controlled by digital bits will provide three operating frequency bands for the power amplifier. In order to implementing the proposed BORN PA, a robust high-power RF switch is presented by using resistive body floating technique and 6-terminal triple-well NMOS. The proposed BORN PA delivers measured saturated output power (Psat) of 21.25/22.25/ 23.0dBm at 960MHz/1317MHz/1750MHz, respectively. Moreover, the proposed BORN PA provides respective 3-dB bandwidth of 400MHz/425MHz/550MHz, output 1-dB compression point (P1dB) of 19.5dBm/20.0dBm/21.0dBm, and power-added efficiency (PAE) of 9/11/13% at three targeted frequency bands, respectively. The promising results show that the proposed BORN PA can be a practical solution for RF multiband applications in terms of the cost and level of integration with other functional blocks of an RF transceiver.

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies.

The geometry of CMOS processes has decreased in a steady pace over the years at the same time as the complexity has increased. Even if there are more requirements on the designer today, the main goal is still the same: to minimize the occupied area and power dissipation. This thesis investigates if a prediction of the costs in future CMOS processes can be made. By implementing several processes on a test circuit we can see a pattern in area and power dissipation when we change to smaller processes. This is done by optimizing a two-stage operational transconductance amplifier on basis of a given specification. A circuit optimization tool evaluates the performance measures and costs. The optimization results from the area and power dissipation is used to present a diagram that shows the decreasing costs with smaller processes and also a prediction of how small the costs will be for future processes. This thesis also presents different optimization tools and a design hexagon that can be used when we struggle with optimization trade-offs.

This dissertation is particularly focused on a novel approach of a wirelessly powered neuromodulation system for chronic patients. The inductively coupled transmitter (TX) and receiver (RX) coils are designed through optimization to achieve maximum efficiency. A power management unit (PMU) consisting of a voltage rectifier, voltage regulator along with a stimulation circuitry is also designed to provide pulse stimulation to genetically modified neurons. For continuous health monitoring purposes, the response from the brain due to stimulation needs to be recorded and transmitted wirelessly outside the brain for analysis. A low-power high-data duty-cycled impulse-radio ultra-wideband (IR-UWB) transmitter is designed and implemented using the standard CMOS process. Another focus of this dissertation is the design of a reverse electrowetting-on-dielectric (REWOD) based energy harvesting circuit for wearable sensor applications which is capable of generating a very low-frequency signal from motion activity such a walking, running, jogging, etc. A commercial off-the-shelf (COTS) based and on-chip based energy harvesting circuit is designed for very low-frequency signals. The experimental results show promising progress towards the advancement in the wirelessly powered neuromodulation system and building the self-powered wearable sensor.